10 commits

Author	SHA1	Message	Date
LDj3SNuD	a5ad1e9a06	Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104) ... * Update AOpCodeTable.cs * Update AInstEmitSimdLogical.cs * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs	2018-04-25 23:20:22 -03:00
MS-DOS1999	76a5972378	Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)	2018-04-19 00:22:12 -03:00
gdkchan	cb29b4303c	[CPU] Fix CNT instruction	2018-04-10 20:58:32 -03:00
LDj3SNuD	873a7cd112	Add Cls Instruction. (#67) ... * Update AInstEmitAlu.cs * Update ASoftFallback.cs * Update AOpCodeTable.cs	2018-03-23 22:06:05 -03:00
gdkchan	92f47d535e	Fix crc32 instruction with size greater than a byte	2018-03-15 18:14:22 -03:00
gdkchan	d067b4d5e0	Remove unused function from CPU	2018-03-14 00:57:07 -03:00
gdkchan	553ba659c4	Add CRC32 instruction and SLI (vector)	2018-03-14 00:12:05 -03:00
gdkchan	efef605b26	Fix REV64 (vector) instruction	2018-03-02 20:24:16 -03:00
gdkchan	035efc913e	Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) instructions, fix for NvFlinger sometimes missing free buffers	2018-02-24 11:19:28 -03:00
emmauss	62b827f474	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/ASoftFallback.cs (Browse further)