1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-11-27 19:32:04 +00:00
Ryujinx/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs
LDj3SNuD 894459fcd7 Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs

* Update ASoftFallback.cs

* Update ASoftFloat.cs

* Update AOpCodeSimdRegElemF.cs

* Update CpuTestSimdIns.cs

* Update CpuTestSimdRegElem.cs

* Create CpuTestSimdRegElemF.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Superseded Fmul_Se Test. Nit.

* Address PR feedback.

* Address PR feedback.

* Update AInstEmitSimdArithmetic.cs

* Update ASoftFallback.cs

* Update AInstEmitAlu.cs

* Update AInstEmitSimdShift.cs
2018-10-13 23:35:16 -03:00

33 lines
807 B
C#

using ChocolArm64.Instruction;
namespace ChocolArm64.Decoder
{
class AOpCodeSimdRegElemF : AOpCodeSimdReg
{
public int Index { get; private set; }
public AOpCodeSimdRegElemF(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
{
switch ((OpCode >> 21) & 3) // sz:L
{
case 0: // H:0
Index = (OpCode >> 10) & 2; // 0, 2
break;
case 1: // H:1
Index = (OpCode >> 10) & 2;
Index++; // 1, 3
break;
case 2: // H
Index = (OpCode >> 11) & 1; // 0, 1
break;
default: Emitter = AInstEmit.Und; return;
}
}
}
}