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Ryujinx/ChocolArm64/Instruction
LDj3SNuD 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)
* Update AILEmitterCtx.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdShift.cs
2018-10-25 19:10:41 -03:00
..
ACryptoHelper.cs Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 2018-08-20 01:20:26 -03:00
AInst.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
AInstEmitAlu.cs Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) 2018-10-13 23:35:16 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs Implement SvcGetThreadContext3 2018-06-26 01:10:15 -03:00
AInstEmitFlow.cs Remove cold methods from the CPU cache (#224) 2018-09-19 17:07:56 -03:00
AInstEmitHash.cs Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183) 2018-06-25 22:32:29 -03:00
AInstEmitMemory.cs Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code 2018-06-02 11:44:52 -03:00
AInstEmitMemoryEx.cs Thread scheduler rewrite (#393) 2018-09-18 20:36:43 -03:00
AInstEmitMemoryHelper.cs More flexible memory manager (#307) 2018-08-15 15:59:51 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) 2018-10-25 19:10:41 -03:00
AInstEmitSimdCmp.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
AInstEmitSimdCrypto.cs Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365) 2018-08-20 01:20:26 -03:00
AInstEmitSimdCvt.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
AInstEmitSimdHash.cs Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352) 2018-08-16 21:44:44 -03:00
AInstEmitSimdHelper.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
AInstEmitSimdLogical.cs Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) 2018-09-26 23:30:21 -03:00
AInstEmitSimdMemory.cs Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) 2018-07-14 13:13:02 -03:00
AInstEmitSimdMove.cs Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449) 2018-10-13 23:35:16 -03:00
AInstEmitSimdShift.cs Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) 2018-10-25 19:10:41 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now) 2018-05-26 17:50:47 -03:00
ASoftFallback.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
ASoftFloat.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00
AVectorHelper.cs Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468) 2018-10-23 11:12:45 -03:00