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ACryptoHelper.cs
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Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
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2018-08-20 01:20:26 -03:00 |
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AInst.cs
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Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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2018-05-26 17:50:47 -03:00 |
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AInstEmitAlu.cs
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Remove broken adds/cmn with condition check optimization (#218)
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2018-07-03 21:54:05 -03:00 |
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AInstEmitAluHelper.cs
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AInstEmitBfm.cs
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AInstEmitCcmp.cs
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AInstEmitCsel.cs
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AInstEmitException.cs
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Implement SvcGetThreadContext3
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2018-06-26 01:10:15 -03:00 |
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AInstEmitFlow.cs
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Remove cold methods from the CPU cache (#224)
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2018-09-19 17:07:56 -03:00 |
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AInstEmitHash.cs
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
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2018-06-25 22:32:29 -03:00 |
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AInstEmitMemory.cs
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Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
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2018-06-02 11:44:52 -03:00 |
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AInstEmitMemoryEx.cs
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Thread scheduler rewrite (#393)
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2018-09-18 20:36:43 -03:00 |
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AInstEmitMemoryHelper.cs
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More flexible memory manager (#307)
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2018-08-15 15:59:51 -03:00 |
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AInstEmitMove.cs
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AInstEmitMul.cs
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AInstEmitSimdArithmetic.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdCmp.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdCrypto.cs
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Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
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2018-08-20 01:20:26 -03:00 |
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AInstEmitSimdCvt.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdHash.cs
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Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
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2018-08-16 21:44:44 -03:00 |
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AInstEmitSimdHelper.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdLogical.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdMemory.cs
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Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
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2018-07-14 13:13:02 -03:00 |
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AInstEmitSimdMove.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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AInstEmitSimdShift.cs
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Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
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2018-09-17 01:54:05 -03:00 |
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AInstEmitSystem.cs
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AInstEmitter.cs
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AInstInterpreter.cs
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Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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2018-05-26 17:50:47 -03:00 |
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ASoftFallback.cs
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Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
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2018-09-08 14:24:29 -03:00 |
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ASoftFloat.cs
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Fix silly copy/paste error on float variant of the FMINNM instruction
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2018-08-05 18:56:30 -03:00 |
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AVectorHelper.cs
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Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
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2018-09-26 23:30:21 -03:00 |
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