LDj3SNuD 430ba6da65 CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) ... * Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. * Add Clmul fast path for the 128 bits variant. * Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant. * Add slow path, both variants. Fix V128 Shl/Shr when shift = 0. * A32: Add Vmull_I P64 variant (slow path); not tested. * A32: Add Vmull_I_P8_P64 Test and fix P64 variant.		2021-01-04 23:45:54 +01:00
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Aarch32Mode.cs
ExecutionContext.cs
ExecutionMode.cs
FPCR.cs
FPException.cs
FPRoundingMode.cs
FPSR.cs
FPState.cs
FPType.cs
InstExceptionEventArgs.cs
InstUndefinedEventArgs.cs
NativeContext.cs
PState.cs
RegisterAlias.cs
RegisterConsts.cs
V128.cs