mirrors/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-11 23:02:02 +00:00
Code Issues Releases Activity
Ryujinx/ARMeilleure/Translation/PTC
History
LDj3SNuD 0679084f11
CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650) 
* net5.0

* CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Switch to .NET 5.0.

Nits.

Tests performed successfully in both debug and release mode (for all instructions involved).

* Address comment.

* Update appveyor.yml

* Revert "Update appveyor.yml"

This reverts commit 27cdd59e8b.

* Remove Assembler CpuId.

* Update appveyor.yml

* Address comment.
2020-11-18 19:35:54 +01:00
..
EncodingCache.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
Ptc.cs CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650) 2020-11-18 19:35:54 +01:00
PtcInfo.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
PtcJumpTable.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
PtcProfiler.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
PtcState.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
RelocEntry.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00