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https://github.com/Ryujinx/Ryujinx.git
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98e05ee4b7
* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
58 lines
1.7 KiB
C#
58 lines
1.7 KiB
C#
using ARMeilleure.Instructions;
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using System;
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namespace ARMeilleure.Decoders
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{
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class OpCodeT16MemImm5 : OpCodeT16, IOpCode32Mem
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{
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public int Rt { get; }
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public int Rn { get; }
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public bool WBack => false;
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public bool IsLoad { get; }
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public bool Index => true;
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public bool Add => true;
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public int Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemImm5(inst, address, opCode);
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public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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Rt = (opCode >> 0) & 7;
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Rn = (opCode >> 3) & 7;
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switch (inst.Name)
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{
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case InstName.Ldr:
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case InstName.Ldrb:
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case InstName.Ldrh:
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IsLoad = true;
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break;
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case InstName.Str:
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case InstName.Strb:
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case InstName.Strh:
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IsLoad = false;
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break;
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}
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switch (inst.Name)
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{
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case InstName.Str:
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case InstName.Ldr:
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Immediate = ((opCode >> 6) & 0x1f) << 2;
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break;
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case InstName.Strb:
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case InstName.Ldrb:
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Immediate = ((opCode >> 6) & 0x1f);
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break;
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case InstName.Strh:
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case InstName.Ldrh:
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Immediate = ((opCode >> 6) & 0x1f) << 1;
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break;
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default:
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throw new InvalidOperationException();
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}
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}
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}
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}
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