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Ryujinx/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693) 
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

673 lines
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C#
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#define SimdCvt
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdCvt")]
public sealed class CpuTestSimdCvt : CpuTest
{
#if SimdCvt
#region "ValueSource (Types)"
private static uint[] _W_()
{
return new uint[] { 0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu };
}
private static ulong[] _X_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static IEnumerable<ulong> _1S_F_WX_()
{
// int
yield return 0x00000000CF000001ul; // -2.1474839E9f (-2147483904)
yield return 0x00000000CF000000ul; // -2.14748365E9f (-2147483648)
yield return 0x00000000CEFFFFFFul; // -2.14748352E9f (-2147483520)
yield return 0x000000004F000001ul; // 2.1474839E9f (2147483904)
yield return 0x000000004F000000ul; // 2.14748365E9f (2147483648)
yield return 0x000000004EFFFFFFul; // 2.14748352E9f (2147483520)
// long
yield return 0x00000000DF000001ul; // -9.223373E18f (-9223373136366403584)
yield return 0x00000000DF000000ul; // -9.223372E18f (-9223372036854775808)
yield return 0x00000000DEFFFFFFul; // -9.2233715E18f (-9223371487098961920)
yield return 0x000000005F000001ul; // 9.223373E18f (9223373136366403584)
yield return 0x000000005F000000ul; // 9.223372E18f (9223372036854775808)
yield return 0x000000005EFFFFFFul; // 9.2233715E18f (9223371487098961920)
// uint
yield return 0x000000004F800001ul; // 4.2949678E9f (4294967808)
yield return 0x000000004F800000ul; // 4.2949673E9f (4294967296)
yield return 0x000000004F7FFFFFul; // 4.29496704E9f (4294967040)
// ulong
yield return 0x000000005F800001ul; // 1.8446746E19f (18446746272732807168)
yield return 0x000000005F800000ul; // 1.8446744E19f (18446744073709551616)
yield return 0x000000005F7FFFFFul; // 1.8446743E19f (18446742974197923840)
yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
yield return 0x0000000080800000ul; // -Min Normal
yield return 0x00000000807FFFFFul; // -Max Subnormal
yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
yield return 0x0000000000800000ul; // +Min Normal
yield return 0x00000000007FFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
if (!NoZeros)
{
yield return 0x0000000080000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
if (!NoInfs)
{
yield return 0x00000000FF800000ul; // -Infinity
yield return 0x000000007F800000ul; // +Infinity
}
if (!NoNaNs)
{
yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
}
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong grbg = TestContext.CurrentContext.Random.NextUInt();
ulong rnd1 = (uint)BitConverter.SingleToInt32Bits(
(float)((int)TestContext.CurrentContext.Random.NextUInt()));
ulong rnd2 = (uint)BitConverter.SingleToInt32Bits(
(float)((long)TestContext.CurrentContext.Random.NextULong()));
ulong rnd3 = (uint)BitConverter.SingleToInt32Bits(
(float)((uint)TestContext.CurrentContext.Random.NextUInt()));
ulong rnd4 = (uint)BitConverter.SingleToInt32Bits(
(float)((ulong)TestContext.CurrentContext.Random.NextULong()));
ulong rnd5 = GenNormalS();
ulong rnd6 = GenSubnormalS();
yield return (grbg << 32) | rnd1;
yield return (grbg << 32) | rnd2;
yield return (grbg << 32) | rnd3;
yield return (grbg << 32) | rnd4;
yield return (grbg << 32) | rnd5;
yield return (grbg << 32) | rnd6;
}
}
private static IEnumerable<ulong> _1D_F_WX_()
{
// int
yield return 0xC1E0000000200000ul; // -2147483649.0000000d (-2147483649)
yield return 0xC1E0000000000000ul; // -2147483648.0000000d (-2147483648)
yield return 0xC1DFFFFFFFC00000ul; // -2147483647.0000000d (-2147483647)
yield return 0x41E0000000200000ul; // 2147483649.0000000d (2147483649)
yield return 0x41E0000000000000ul; // 2147483648.0000000d (2147483648)
yield return 0x41DFFFFFFFC00000ul; // 2147483647.0000000d (2147483647)
// long
yield return 0xC3E0000000000001ul; // -9.2233720368547780E18d (-9223372036854778000)
yield return 0xC3E0000000000000ul; // -9.2233720368547760E18d (-9223372036854776000)
yield return 0xC3DFFFFFFFFFFFFFul; // -9.2233720368547750E18d (-9223372036854775000)
yield return 0x43E0000000000001ul; // 9.2233720368547780E18d (9223372036854778000)
yield return 0x43E0000000000000ul; // 9.2233720368547760E18d (9223372036854776000)
yield return 0x43DFFFFFFFFFFFFFul; // 9.2233720368547750E18d (9223372036854775000)
// uint
yield return 0x41F0000000100000ul; // 4294967297.0000000d (4294967297)
yield return 0x41F0000000000000ul; // 4294967296.0000000d (4294967296)
yield return 0x41EFFFFFFFE00000ul; // 4294967295.0000000d (4294967295)
// ulong
yield return 0x43F0000000000001ul; // 1.8446744073709556e19d (18446744073709556000)
yield return 0x43F0000000000000ul; // 1.8446744073709552E19d (18446744073709552000)
yield return 0x43EFFFFFFFFFFFFFul; // 1.8446744073709550e19d (18446744073709550000)
yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal (double.MinValue)
yield return 0x8010000000000000ul; // -Min Normal
yield return 0x800FFFFFFFFFFFFFul; // -Max Subnormal
yield return 0x8000000000000001ul; // -Min Subnormal (-double.Epsilon)
yield return 0x7FEFFFFFFFFFFFFFul; // +Max Normal (double.MaxValue)
yield return 0x0010000000000000ul; // +Min Normal
yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
if (!NoZeros)
{
yield return 0x8000000000000000ul; // -Zero
yield return 0x0000000000000000ul; // +Zero
}
if (!NoInfs)
{
yield return 0xFFF0000000000000ul; // -Infinity
yield return 0x7FF0000000000000ul; // +Infinity
}
if (!NoNaNs)
{
yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload)
yield return 0x7FF8000000000000ul; // +QNaN (all zeros payload) (-double.NaN) (DefaultNaN)
yield return 0x7FF7FFFFFFFFFFFFul; // +SNaN (all ones payload)
}
for (int cnt = 1; cnt <= RndCnt; cnt++)
{
ulong rnd1 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((int)TestContext.CurrentContext.Random.NextUInt()));
ulong rnd2 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((long)TestContext.CurrentContext.Random.NextULong()));
ulong rnd3 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((uint)TestContext.CurrentContext.Random.NextUInt()));
ulong rnd4 = (ulong)BitConverter.DoubleToInt64Bits(
(double)((ulong)TestContext.CurrentContext.Random.NextULong()));
ulong rnd5 = GenNormalD();
ulong rnd6 = GenSubnormalD();
yield return rnd1;
yield return rnd2;
yield return rnd3;
yield return rnd4;
yield return rnd5;
yield return rnd6;
}
}
#endregion
#region "ValueSource (Opcodes)"
private static uint[] _F_Cvt_AMPZ_SU_Gp_SW_()
{
return new uint[]
{
0x1E240000u, // FCVTAS W0, S0
0x1E250000u, // FCVTAU W0, S0
0x1E300000u, // FCVTMS W0, S0
0x1E310000u, // FCVTMU W0, S0
0x1E280000u, // FCVTPS W0, S0
0x1E290000u, // FCVTPU W0, S0
0x1E380000u, // FCVTZS W0, S0
0x1E390000u // FCVTZU W0, S0
};
}
private static uint[] _F_Cvt_AMPZ_SU_Gp_SX_()
{
return new uint[]
{
0x9E240000u, // FCVTAS X0, S0
0x9E250000u, // FCVTAU X0, S0
0x9E300000u, // FCVTMS X0, S0
0x9E310000u, // FCVTMU X0, S0
0x9E280000u, // FCVTPS X0, S0
0x9E290000u, // FCVTPU X0, S0
0x9E380000u, // FCVTZS X0, S0
0x9E390000u // FCVTZU X0, S0
};
}
private static uint[] _F_Cvt_AMPZ_SU_Gp_DW_()
{
return new uint[]
{
0x1E640000u, // FCVTAS W0, D0
0x1E650000u, // FCVTAU W0, D0
0x1E700000u, // FCVTMS W0, D0
0x1E710000u, // FCVTMU W0, D0
0x1E680000u, // FCVTPS W0, D0
0x1E690000u, // FCVTPU W0, D0
0x1E780000u, // FCVTZS W0, D0
0x1E790000u // FCVTZU W0, D0
};
}
private static uint[] _F_Cvt_AMPZ_SU_Gp_DX_()
{
return new uint[]
{
0x9E640000u, // FCVTAS X0, D0
0x9E650000u, // FCVTAU X0, D0
0x9E700000u, // FCVTMS X0, D0
0x9E710000u, // FCVTMU X0, D0
0x9E680000u, // FCVTPS X0, D0
0x9E690000u, // FCVTPU X0, D0
0x9E780000u, // FCVTZS X0, D0
0x9E790000u // FCVTZU X0, D0
};
}
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SW_()
{
return new uint[]
{
0x1E188000u, // FCVTZS W0, S0, #32
0x1E198000u // FCVTZU W0, S0, #32
};
}
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_SX_()
{
return new uint[]
{
0x9E180000u, // FCVTZS X0, S0, #64
0x9E190000u // FCVTZU X0, S0, #64
};
}
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DW_()
{
return new uint[]
{
0x1E588000u, // FCVTZS W0, D0, #32
0x1E598000u // FCVTZU W0, D0, #32
};
}
private static uint[] _F_Cvt_Z_SU_Gp_Fixed_DX_()
{
return new uint[]
{
0x9E580000u, // FCVTZS X0, D0, #64
0x9E590000u // FCVTZU X0, D0, #64
};
}
private static uint[] _SU_Cvt_F_Gp_WS_()
{
return new uint[]
{
0x1E220000u, // SCVTF S0, W0
0x1E230000u // UCVTF S0, W0
};
}
private static uint[] _SU_Cvt_F_Gp_WD_()
{
return new uint[]
{
0x1E620000u, // SCVTF D0, W0
0x1E630000u // UCVTF D0, W0
};
}
private static uint[] _SU_Cvt_F_Gp_XS_()
{
return new uint[]
{
0x9E220000u, // SCVTF S0, X0
0x9E230000u // UCVTF S0, X0
};
}
private static uint[] _SU_Cvt_F_Gp_XD_()
{
return new uint[]
{
0x9E620000u, // SCVTF D0, X0
0x9E630000u // UCVTF D0, X0
};
}
private static uint[] _SU_Cvt_F_Gp_Fixed_WS_()
{
return new uint[]
{
0x1E028000u, // SCVTF S0, W0, #32
0x1E038000u // UCVTF S0, W0, #32
};
}
private static uint[] _SU_Cvt_F_Gp_Fixed_WD_()
{
return new uint[]
{
0x1E428000u, // SCVTF D0, W0, #32
0x1E438000u // UCVTF D0, W0, #32
};
}
private static uint[] _SU_Cvt_F_Gp_Fixed_XS_()
{
return new uint[]
{
0x9E020000u, // SCVTF S0, X0, #64
0x9E030000u // UCVTF S0, X0, #64
};
}
private static uint[] _SU_Cvt_F_Gp_Fixed_XD_()
{
return new uint[]
{
0x9E420000u, // SCVTF D0, X0, #64
0x9E430000u // UCVTF D0, X0, #64
};
}
#endregion
private const int RndCnt = 2;
private const int RndCntFBits = 2;
private static readonly bool NoZeros = false;
private static readonly bool NoInfs = false;
private static readonly bool NoNaNs = false;
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_SW([ValueSource("_F_Cvt_AMPZ_SU_Gp_SW_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
uint w31 = TestContext.CurrentContext.Random.NextUInt();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_SX([ValueSource("_F_Cvt_AMPZ_SU_Gp_SX_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x31: x31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_DW([ValueSource("_F_Cvt_AMPZ_SU_Gp_DW_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
uint w31 = TestContext.CurrentContext.Random.NextUInt();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_AMPZ_SU_Gp_DX([ValueSource("_F_Cvt_AMPZ_SU_Gp_DX_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x31: x31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_SW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SW_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
uint w31 = TestContext.CurrentContext.Random.NextUInt();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_SX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_SX_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1S_F_WX_")] ulong a,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x31: x31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_DW([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DW_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x0 = (ulong)TestContext.CurrentContext.Random.NextUInt() << 32;
uint w31 = TestContext.CurrentContext.Random.NextUInt();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x0: x0, x31: w31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void F_Cvt_Z_SU_Gp_Fixed_DX([ValueSource("_F_Cvt_Z_SU_Gp_Fixed_DX_")] uint opcodes,
[Values(0u, 31u)] uint rd,
[Values(1u)] uint rn,
[ValueSource("_1D_F_WX_")] ulong a,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, x31: x31, v1: v1);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WS([ValueSource("_SU_Cvt_F_Gp_WS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_WD([ValueSource("_SU_Cvt_F_Gp_WD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XS([ValueSource("_SU_Cvt_F_Gp_XS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_XD([ValueSource("_SU_Cvt_F_Gp_XD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn)
{
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_WS([ValueSource("_SU_Cvt_F_Gp_Fixed_WS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_WD([ValueSource("_SU_Cvt_F_Gp_Fixed_WD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_W_")] [Random(RndCnt)] uint wn,
[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
uint w31 = TestContext.CurrentContext.Random.NextUInt();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: wn, x31: w31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_XS([ValueSource("_SU_Cvt_F_Gp_Fixed_XS_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
public void SU_Cvt_F_Gp_Fixed_XD([ValueSource("_SU_Cvt_F_Gp_Fixed_XD_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource("_X_")] [Random(RndCnt)] ulong xn,
[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
{
uint scale = (64u - fBits) & 0x3Fu;
opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcodes |= (scale << 10);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE1(z);
SingleOpcode(opcodes, x1: xn, x31: x31, v0: v0);
CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
}
#endif
}
}
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