mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-27 08:32:01 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
316 lines
14 KiB
C#
316 lines
14 KiB
C#
#define SimdTbl
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdTbl")]
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public sealed class CpuTestSimdTbl : CpuTest
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{
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#if SimdTbl
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#region "Helper methods"
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private static ulong GenIdxsForTbls(int regs)
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{
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const byte idxInRngMin = (byte)0;
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byte idxInRngMax = (byte)((16 * regs) - 1);
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byte idxOutRngMin = (byte) (16 * regs);
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const byte idxOutRngMax = (byte)255;
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ulong idxs = 0ul;
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for (int cnt = 1; cnt <= 8; cnt++)
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{
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ulong idxInRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax);
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ulong idxOutRng = (ulong)TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax);
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ulong idx = TestContext.CurrentContext.Random.NextBool() ? idxInRng : idxOutRng;
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idxs = (idxs << 8) | idx;
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}
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return idxs;
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}
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _8B_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<ulong> _GenIdxsForTbl1_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 1);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl2_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 2);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl3_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 3);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl4_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 4);
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _SingleRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E000000u, // TBL V0.8B, { V0.16B }, V0.8B
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};
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}
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private static uint[] _TwoRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E002000u, // TBL V0.8B, { V0.16B, V1.16B }, V0.8B
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};
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}
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private static uint[] _ThreeRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E004000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
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};
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}
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private static uint[] _FourRegTbl_V_8B_16B_()
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{
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return new uint[]
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{
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0x0E006000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
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};
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}
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#endregion
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private const int RndCntTbls = 2;
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private const int RndCntIdxs = 2;
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B }, <Vm>.<Ta>")]
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public void SingleRegTbl_V_8B_16B([ValueSource("_SingleRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(2u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_GenIdxsForTbl1_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>")]
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public void TwoRegTbl_V_8B_16B([ValueSource("_TwoRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(3u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B }, <Vm>.<Ta>")]
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public void Mod_TwoRegTbl_V_8B_16B([ValueSource("_TwoRegTbl_V_8B_16B_")] uint opcodes,
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[Values(30u, 1u)] uint rd,
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[Values(31u)] uint rn,
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[Values(1u, 30u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_GenIdxsForTbl2_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>")]
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public void ThreeRegTbl_V_8B_16B([ValueSource("_ThreeRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(4u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
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[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(table2, table2);
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V128 v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B }, <Vm>.<Ta>")]
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public void Mod_ThreeRegTbl_V_8B_16B([ValueSource("_ThreeRegTbl_V_8B_16B_")] uint opcodes,
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[Values(30u, 2u)] uint rd,
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[Values(31u)] uint rn,
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[Values(2u, 30u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
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[ValueSource("_GenIdxsForTbl3_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(table2, table2);
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V128 v2 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>")]
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public void FourRegTbl_V_8B_16B([ValueSource("_FourRegTbl_V_8B_16B_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(5u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
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[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(table2, table2);
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V128 v4 = MakeVectorE0E1(table3, table3);
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V128 v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("TBL <Vd>.<Ta>, { <Vn>.16B, <Vn+1>.16B, <Vn+2>.16B, <Vn+3>.16B }, <Vm>.<Ta>")]
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public void Mod_FourRegTbl_V_8B_16B([ValueSource("_FourRegTbl_V_8B_16B_")] uint opcodes,
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[Values(30u, 3u)] uint rd,
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[Values(31u)] uint rn,
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[Values(3u, 30u)] uint rm,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table0,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table1,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table2,
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[ValueSource("_8B_")] [Random(RndCntTbls)] ulong table3,
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[ValueSource("_GenIdxsForTbl4_")] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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ulong z = TestContext.CurrentContext.Random.NextULong();
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(table2, table2);
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V128 v2 = MakeVectorE0E1(table3, table3);
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V128 v3 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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