mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-27 15:42:04 +00:00
d2bb458b51
* Better implementation of the DMA pusher, misc fixes * Remove some debug code * Correct RGBX8 format * Add support for linked Texture Sampler Control * Attempt to fix upside down screen issue
161 lines
No EOL
4.5 KiB
C#
161 lines
No EOL
4.5 KiB
C#
using Ryujinx.Graphics.Memory;
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using Ryujinx.Graphics.Texture;
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using System.Collections.Generic;
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namespace Ryujinx.Graphics
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{
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class NvGpuEngineP2mf : INvGpuEngine
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{
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public int[] Registers { get; private set; }
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private NvGpu Gpu;
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private Dictionary<int, NvGpuMethod> Methods;
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private int CopyStartX;
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private int CopyStartY;
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private int CopyWidth;
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private int CopyHeight;
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private int CopyGobBlockHeight;
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private long CopyAddress;
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private int CopyOffset;
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private int CopySize;
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private bool CopyLinear;
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private byte[] Buffer;
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public NvGpuEngineP2mf(NvGpu Gpu)
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{
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this.Gpu = Gpu;
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Registers = new int[0x80];
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Methods = new Dictionary<int, NvGpuMethod>();
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void AddMethod(int Meth, int Count, int Stride, NvGpuMethod Method)
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{
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while (Count-- > 0)
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{
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Methods.Add(Meth, Method);
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Meth += Stride;
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}
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}
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AddMethod(0x6c, 1, 1, Execute);
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AddMethod(0x6d, 1, 1, PushData);
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}
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public void CallMethod(NvGpuVmm Vmm, GpuMethodCall MethCall)
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{
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if (Methods.TryGetValue(MethCall.Method, out NvGpuMethod Method))
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{
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Method(Vmm, MethCall);
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}
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else
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{
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WriteRegister(MethCall);
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}
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}
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private void Execute(NvGpuVmm Vmm, GpuMethodCall MethCall)
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{
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//TODO: Some registers and copy modes are still not implemented.
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int Control = MethCall.Argument;
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long DstAddress = MakeInt64From2xInt32(NvGpuEngineP2mfReg.DstAddress);
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int DstPitch = ReadRegister(NvGpuEngineP2mfReg.DstPitch);
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int DstBlkDim = ReadRegister(NvGpuEngineP2mfReg.DstBlockDim);
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int DstX = ReadRegister(NvGpuEngineP2mfReg.DstX);
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int DstY = ReadRegister(NvGpuEngineP2mfReg.DstY);
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int DstWidth = ReadRegister(NvGpuEngineP2mfReg.DstWidth);
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int DstHeight = ReadRegister(NvGpuEngineP2mfReg.DstHeight);
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int LineLengthIn = ReadRegister(NvGpuEngineP2mfReg.LineLengthIn);
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int LineCount = ReadRegister(NvGpuEngineP2mfReg.LineCount);
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CopyLinear = (Control & 1) != 0;
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CopyGobBlockHeight = 1 << ((DstBlkDim >> 4) & 0xf);
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CopyStartX = DstX;
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CopyStartY = DstY;
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CopyWidth = DstWidth;
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CopyHeight = DstHeight;
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CopyAddress = DstAddress;
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CopyOffset = 0;
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CopySize = LineLengthIn * LineCount;
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Buffer = new byte[CopySize];
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}
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private void PushData(NvGpuVmm Vmm, GpuMethodCall MethCall)
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{
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if (Buffer == null)
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{
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return;
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}
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for (int Shift = 0; Shift < 32 && CopyOffset < CopySize; Shift += 8, CopyOffset++)
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{
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Buffer[CopyOffset] = (byte)(MethCall.Argument >> Shift);
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}
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if (MethCall.IsLastCall)
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{
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if (CopyLinear)
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{
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Vmm.WriteBytes(CopyAddress, Buffer);
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}
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else
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{
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BlockLinearSwizzle Swizzle = new BlockLinearSwizzle(CopyWidth, 1, CopyGobBlockHeight);
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int SrcOffset = 0;
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for (int Y = CopyStartY; Y < CopyHeight && SrcOffset < CopySize; Y++)
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for (int X = CopyStartX; X < CopyWidth && SrcOffset < CopySize; X++)
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{
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int DstOffset = Swizzle.GetSwizzleOffset(X, Y);
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Vmm.WriteByte(CopyAddress + DstOffset, Buffer[SrcOffset++]);
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}
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}
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Buffer = null;
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}
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}
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private long MakeInt64From2xInt32(NvGpuEngineP2mfReg Reg)
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{
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return
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(long)Registers[(int)Reg + 0] << 32 |
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(uint)Registers[(int)Reg + 1];
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}
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private void WriteRegister(GpuMethodCall MethCall)
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{
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Registers[MethCall.Method] = MethCall.Argument;
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}
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private int ReadRegister(NvGpuEngineP2mfReg Reg)
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{
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return Registers[(int)Reg];
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}
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private void WriteRegister(NvGpuEngineP2mfReg Reg, int Value)
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{
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Registers[(int)Reg] = Value;
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}
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}
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} |