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https://github.com/Ryujinx/Ryujinx.git
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b2b736abc2
* Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing
138 lines
No EOL
4 KiB
C#
138 lines
No EOL
4 KiB
C#
using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.Translation;
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using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
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using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
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namespace Ryujinx.Graphics.Shader.Instructions
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{
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static partial class InstEmit
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{
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public static void Ald(EmitterContext context)
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{
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OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
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Operand[] elems = new Operand[op.Count];
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for (int index = 0; index < op.Count; index++)
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{
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Operand src = Attribute(op.AttributeOffset + index * 4);
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context.Copy(elems[index] = Local(), src);
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}
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for (int index = 0; index < op.Count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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context.Copy(Register(rd), elems[index]);
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}
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}
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public static void Ast(EmitterContext context)
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{
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OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
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for (int index = 0; index < op.Count; index++)
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{
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if (op.Rd.Index + index > RegisterConsts.RegisterZeroIndex)
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{
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break;
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}
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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Operand dest = Attribute(op.AttributeOffset + index * 4);
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context.Copy(dest, Register(rd));
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}
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}
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public static void Ipa(EmitterContext context)
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{
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OpCodeIpa op = (OpCodeIpa)context.CurrOp;
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Operand srcA = new Operand(OperandType.Attribute, op.AttributeOffset);
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Operand srcB = GetSrcB(context);
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context.Copy(GetDest(context), srcA);
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}
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public static void Ldc(EmitterContext context)
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{
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OpCodeLdc op = (OpCodeLdc)context.CurrOp;
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if (op.Size > IntegerSize.B64)
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{
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// TODO: Warning.
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}
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bool isSmallInt = op.Size < IntegerSize.B32;
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int count = op.Size == IntegerSize.B64 ? 2 : 1;
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Operand baseOffset = context.Copy(GetSrcA(context));
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for (int index = 0; index < count; index++)
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{
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Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
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if (rd.IsRZ)
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{
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break;
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}
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Operand offset = context.IAdd(baseOffset, Const((op.Offset + index) * 4));
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Operand value = context.LoadConstant(Const(op.Slot), offset);
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if (isSmallInt)
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{
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Operand shift = context.BitwiseAnd(baseOffset, Const(3));
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value = context.ShiftRightU32(value, shift);
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switch (op.Size)
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{
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case IntegerSize.U8: value = ZeroExtendTo32(context, value, 8); break;
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case IntegerSize.U16: value = ZeroExtendTo32(context, value, 16); break;
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case IntegerSize.S8: value = SignExtendTo32(context, value, 8); break;
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case IntegerSize.S16: value = SignExtendTo32(context, value, 16); break;
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}
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}
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context.Copy(Register(rd), value);
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}
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}
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public static void Out(EmitterContext context)
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{
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OpCode op = context.CurrOp;
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bool emit = op.RawOpCode.Extract(39);
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bool cut = op.RawOpCode.Extract(40);
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if (!(emit || cut))
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{
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// TODO: Warning.
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}
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if (emit)
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{
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context.EmitVertex();
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}
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if (cut)
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{
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context.EndPrimitive();
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}
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}
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}
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} |