mirror of
https://github.com/Ryujinx/Ryujinx.git
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8a7d99cdea
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
82 lines
No EOL
2 KiB
C#
82 lines
No EOL
2 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmitAluHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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private enum CcmpOp
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{
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Cmp,
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Cmn
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}
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public static void Ccmn(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmn);
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public static void Ccmp(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmp);
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private static void EmitCcmp(ILEmitterCtx context, CcmpOp cmpOp)
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{
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OpCodeCcmp64 op = (OpCodeCcmp64)context.CurrOp;
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ILLabel lblTrue = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.EmitCondBranch(lblTrue, op.Cond);
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context.EmitLdc_I4((op.Nzcv >> 0) & 1);
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context.EmitStflg((int)PState.VBit);
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context.EmitLdc_I4((op.Nzcv >> 1) & 1);
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context.EmitStflg((int)PState.CBit);
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context.EmitLdc_I4((op.Nzcv >> 2) & 1);
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context.EmitStflg((int)PState.ZBit);
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context.EmitLdc_I4((op.Nzcv >> 3) & 1);
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context.EmitStflg((int)PState.NBit);
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context.Emit(OpCodes.Br_S, lblEnd);
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context.MarkLabel(lblTrue);
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EmitAluLoadOpers(context);
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if (cmpOp == CcmpOp.Cmp)
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{
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context.Emit(OpCodes.Sub);
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context.EmitZnFlagCheck();
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EmitSubsCCheck(context);
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EmitSubsVCheck(context);
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}
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else if (cmpOp == CcmpOp.Cmn)
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{
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context.Emit(OpCodes.Add);
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context.EmitZnFlagCheck();
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EmitAddsCCheck(context);
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EmitAddsVCheck(context);
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}
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else
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{
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throw new ArgumentException(nameof(cmpOp));
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}
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context.Emit(OpCodes.Pop);
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context.MarkLabel(lblEnd);
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}
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}
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} |