mirror of
https://github.com/Ryujinx/Ryujinx.git
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3edb66f389
* Add background translation to the CPU * Do not use a separate thread for translation, implement 2 tiers translation * Remove unnecessary usings * Lower MinCallCountForReJit * Remove unused variable
189 lines
No EOL
5.3 KiB
C#
189 lines
No EOL
5.3 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void B(AILEmitterCtx Context)
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{
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AOpCodeBImmAl Op = (AOpCodeBImmAl)Context.CurrOp;
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if (Context.CurrBlock.Branch != null)
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{
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Context.Emit(OpCodes.Br, Context.GetLabel(Op.Imm));
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}
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else
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{
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Context.EmitStoreState();
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Context.EmitLdc_I8(Op.Imm);
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Context.Emit(OpCodes.Ret);
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}
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}
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public static void B_Cond(AILEmitterCtx Context)
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{
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AOpCodeBImmCond Op = (AOpCodeBImmCond)Context.CurrOp;
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EmitBranch(Context, Op.Cond);
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}
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public static void Bl(AILEmitterCtx Context)
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{
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AOpCodeBImmAl Op = (AOpCodeBImmAl)Context.CurrOp;
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Context.EmitLdc_I(Op.Position + 4);
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Context.EmitStint(AThreadState.LRIndex);
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Context.EmitStoreState();
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if (Context.TryOptEmitSubroutineCall())
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{
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//Note: the return value of the called method will be placed
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//at the Stack, the return value is always a Int64 with the
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//return address of the function. We check if the address is
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//correct, if it isn't we keep returning until we reach the dispatcher.
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I8(Op.Position + 4);
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AILLabel LblContinue = new AILLabel();
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Context.Emit(OpCodes.Beq_S, LblContinue);
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Context.Emit(OpCodes.Ret);
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Context.MarkLabel(LblContinue);
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Context.Emit(OpCodes.Pop);
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Context.EmitLoadState(Context.CurrBlock.Next);
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}
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else
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{
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Context.EmitLdc_I8(Op.Imm);
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Context.Emit(OpCodes.Ret);
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}
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}
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public static void Blr(AILEmitterCtx Context)
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{
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AOpCodeBReg Op = (AOpCodeBReg)Context.CurrOp;
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Context.EmitLdc_I(Op.Position + 4);
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Context.EmitStint(AThreadState.LRIndex);
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Context.EmitStoreState();
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Context.EmitLdintzr(Op.Rn);
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Context.Emit(OpCodes.Ret);
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}
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public static void Br(AILEmitterCtx Context)
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{
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AOpCodeBReg Op = (AOpCodeBReg)Context.CurrOp;
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Context.EmitStoreState();
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Context.EmitLdintzr(Op.Rn);
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Context.Emit(OpCodes.Ret);
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}
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public static void Cbnz(AILEmitterCtx Context) => EmitCb(Context, OpCodes.Bne_Un);
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public static void Cbz(AILEmitterCtx Context) => EmitCb(Context, OpCodes.Beq);
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private static void EmitCb(AILEmitterCtx Context, OpCode ILOp)
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{
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AOpCodeBImmCmp Op = (AOpCodeBImmCmp)Context.CurrOp;
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Context.EmitLdintzr(Op.Rt);
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Context.EmitLdc_I(0);
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EmitBranch(Context, ILOp);
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}
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public static void Ret(AILEmitterCtx Context)
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{
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Context.EmitStoreState();
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Context.EmitLdint(AThreadState.LRIndex);
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Context.Emit(OpCodes.Ret);
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}
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public static void Tbnz(AILEmitterCtx Context) => EmitTb(Context, OpCodes.Bne_Un);
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public static void Tbz(AILEmitterCtx Context) => EmitTb(Context, OpCodes.Beq);
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private static void EmitTb(AILEmitterCtx Context, OpCode ILOp)
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{
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AOpCodeBImmTest Op = (AOpCodeBImmTest)Context.CurrOp;
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Context.EmitLdintzr(Op.Rt);
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Context.EmitLdc_I(1L << Op.Pos);
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Context.Emit(OpCodes.And);
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Context.EmitLdc_I(0);
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EmitBranch(Context, ILOp);
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}
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private static void EmitBranch(AILEmitterCtx Context, ACond Cond)
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{
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AOpCodeBImm Op = (AOpCodeBImm)Context.CurrOp;
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if (Context.CurrBlock.Next != null &&
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Context.CurrBlock.Branch != null)
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{
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Context.EmitCondBranch(Context.GetLabel(Op.Imm), Cond);
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}
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else
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{
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Context.EmitStoreState();
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AILLabel LblTaken = new AILLabel();
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Context.EmitCondBranch(LblTaken, Cond);
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Context.EmitLdc_I8(Op.Position + 4);
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Context.Emit(OpCodes.Ret);
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Context.MarkLabel(LblTaken);
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Context.EmitLdc_I8(Op.Imm);
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Context.Emit(OpCodes.Ret);
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}
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}
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private static void EmitBranch(AILEmitterCtx Context, OpCode ILOp)
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{
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AOpCodeBImm Op = (AOpCodeBImm)Context.CurrOp;
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if (Context.CurrBlock.Next != null &&
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Context.CurrBlock.Branch != null)
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{
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Context.Emit(ILOp, Context.GetLabel(Op.Imm));
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}
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else
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{
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Context.EmitStoreState();
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AILLabel LblTaken = new AILLabel();
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Context.Emit(ILOp, LblTaken);
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Context.EmitLdc_I8(Op.Position + 4);
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Context.Emit(OpCodes.Ret);
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Context.MarkLabel(LblTaken);
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Context.EmitLdc_I8(Op.Imm);
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Context.Emit(OpCodes.Ret);
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}
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}
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}
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} |