FICTURE7 36ec1bc6c0 Relax block ordering constraints (#1535) ... * Relax block ordering constraints Before `block.Next` had to follow `block.ListNext`, now it does not. Instead `CodeGenerator` will now emit the necessary jump instructions to ensure control flow. This makes control flow and block order modifications easier. It also eliminates some simple cases of redundant branches. * Set PPTC version		2020-09-12 12:32:53 -03:00
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BasicBlock.cs	Relax block ordering constraints (#1535)	2020-09-12 12:32:53 -03:00
Comparison.cs	Improve branch operations (#1442)	2020-08-05 08:52:33 +10:00
IIntrusiveListNode.cs	Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931)	2020-02-17 22:30:54 +01:00
Instruction.cs	Relax block ordering constraints (#1535)	2020-09-12 12:32:53 -03:00
Intrinsic.cs	Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)	2020-07-13 20:48:14 +10:00
IntrinsicOperation.cs
IntrusiveList.cs	Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931)	2020-02-17 22:30:54 +01:00
MemoryOperand.cs	CodeGen Optimisations (LSRA and Translator) (#978)	2020-03-18 22:44:32 +11:00
Multiplier.cs
Node.cs	Fix Node Uses/Assignments (#1376)	2020-07-13 20:20:07 +10:00
Operand.cs	Fix PPTC on Windows 7. (#1369)	2020-07-09 10:45:24 +10:00
OperandHelper.cs	Fix PPTC on Windows 7. (#1369)	2020-07-09 10:45:24 +10:00
OperandKind.cs
OperandType.cs
Operation.cs	CodeGen Optimisations (LSRA and Translator) (#978)	2020-03-18 22:44:32 +11:00
OperationHelper.cs	CodeGen Optimisations (LSRA and Translator) (#978)	2020-03-18 22:44:32 +11:00
PhiNode.cs
Register.cs
RegisterType.cs	Add most of the A32 instruction set to ARMeilleure (#897)	2020-02-24 08:20:40 +11:00