| .. |
|
AInst.cs
|
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
2018-05-26 17:50:47 -03:00 |
|
AInstEmitAlu.cs
|
Remove broken adds/cmn with condition check optimization (#218)
|
2018-07-03 21:54:05 -03:00 |
|
AInstEmitAluHelper.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
|
AInstEmitBfm.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
|
AInstEmitCcmp.cs
|
Split main project into core,graphics and chocolarm4 subproject (#29)
|
2018-02-20 17:09:23 -03:00 |
|
AInstEmitCsel.cs
|
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
|
2018-02-25 22:14:58 -03:00 |
|
AInstEmitException.cs
|
Implement SvcGetThreadContext3
|
2018-06-26 01:10:15 -03:00 |
|
AInstEmitFlow.cs
|
Stub a few services, add support for generating call stacks on the CPU
|
2018-04-22 01:22:46 -03:00 |
|
AInstEmitHash.cs
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
|
2018-06-25 22:32:29 -03:00 |
|
AInstEmitMemory.cs
|
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
|
2018-06-02 11:44:52 -03:00 |
|
AInstEmitMemoryEx.cs
|
Fix some thread sync issues (#172)
|
2018-06-21 23:05:42 -03:00 |
|
AInstEmitMemoryHelper.cs
|
Improved logging (#103)
|
2018-04-24 15:57:39 -03:00 |
|
AInstEmitMove.cs
|
Split main project into core,graphics and chocolarm4 subproject (#29)
|
2018-02-20 17:09:23 -03:00 |
|
AInstEmitMul.cs
|
Split main project into core,graphics and chocolarm4 subproject (#29)
|
2018-02-20 17:09:23 -03:00 |
|
AInstEmitSimdArithmetic.cs
|
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
|
2018-07-15 00:53:26 -03:00 |
|
AInstEmitSimdCmp.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSimdCvt.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSimdHelper.cs
|
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
|
2018-07-15 00:53:26 -03:00 |
|
AInstEmitSimdLogical.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSimdMemory.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSimdMove.cs
|
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
|
2018-07-15 00:53:26 -03:00 |
|
AInstEmitSimdShift.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSystem.cs
|
Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
|
2018-03-13 21:24:32 -03:00 |
|
AInstEmitter.cs
|
Split main project into core,graphics and chocolarm4 subproject (#29)
|
2018-02-20 17:09:23 -03:00 |
|
AInstInterpreter.cs
|
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
2018-05-26 17:50:47 -03:00 |
|
ASoftFallback.cs
|
Improve CountLeadingZeros() algorithm, nits. (#219)
|
2018-07-14 15:07:44 -03:00 |
|
ASoftFloat.cs
|
AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)
|
2018-07-12 15:51:02 -03:00 |
|
AVectorHelper.cs
|
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
|
2018-07-03 03:31:16 -03:00 |
063fae50fe