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https://github.com/Ryujinx/Ryujinx.git
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92d166ecb7
* Enable CPU JIT cache invalidation * Invalidate cache on IC IVAU
164 lines
6.7 KiB
C#
164 lines
6.7 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit
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{
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private const int DczSizeLog2 = 4; // Log2 size in words
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public const int DczSizeInBytes = 4 << DczSizeLog2;
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public static void Hint(ArmEmitterContext context)
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{
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// Execute as no-op.
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}
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public static void Isb(ArmEmitterContext context)
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{
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// Execute as no-op.
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}
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public static void Mrs(ArmEmitterContext context)
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{
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OpCodeSystem op = (OpCodeSystem)context.CurrOp;
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MethodInfo info;
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switch (GetPackedId(op))
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{
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case 0b11_011_0000_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); break;
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case 0b11_011_0000_0000_111: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); break;
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case 0b11_011_0100_0010_000: EmitGetNzcv(context); return;
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case 0b11_011_0100_0100_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcr)); break;
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case 0b11_011_0100_0100_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpsr)); break;
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case 0b11_011_1101_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl0)); break;
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case 0b11_011_1101_0000_011: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr)); break;
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case 0b11_011_1110_0000_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); break;
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case 0b11_011_1110_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
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case 0b11_011_1110_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); break;
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default: throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
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}
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SetIntOrZR(context, op.Rt, context.Call(info));
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}
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public static void Msr(ArmEmitterContext context)
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{
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OpCodeSystem op = (OpCodeSystem)context.CurrOp;
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MethodInfo info;
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switch (GetPackedId(op))
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{
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case 0b11_011_0100_0010_000: EmitSetNzcv(context); return;
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case 0b11_011_0100_0100_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpcr)); break;
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case 0b11_011_0100_0100_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsr)); break;
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case 0b11_011_1101_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl0)); break;
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default: throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
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}
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context.Call(info, GetIntOrZR(context, op.Rt));
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}
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public static void Nop(ArmEmitterContext context)
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{
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// Do nothing.
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}
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public static void Sys(ArmEmitterContext context)
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{
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// This instruction is used to do some operations on the CPU like cache invalidation,
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// address translation and the like.
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// We treat it as no-op here since we don't have any cache being emulated anyway.
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OpCodeSystem op = (OpCodeSystem)context.CurrOp;
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switch (GetPackedId(op))
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{
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case 0b11_011_0111_0100_001:
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{
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// DC ZVA
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Operand t = GetIntOrZR(context, op.Rt);
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for (long offset = 0; offset < DczSizeInBytes; offset += 8)
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{
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Operand address = context.Add(t, Const(offset));
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InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3);
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}
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break;
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}
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// No-op
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case 0b11_011_0111_1110_001: // DC CIVAC
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break;
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case 0b11_011_0111_0101_001: // IC IVAU
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Operand target = Register(op.Rt, RegisterType.Integer, OperandType.I64);
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context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.InvalidateCacheLine)), target);
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break;
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}
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}
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private static int GetPackedId(OpCodeSystem op)
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{
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int id;
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id = op.Op2 << 0;
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id |= op.CRm << 3;
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id |= op.CRn << 7;
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id |= op.Op1 << 11;
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id |= op.Op0 << 14;
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return id;
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}
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private static void EmitGetNzcv(ArmEmitterContext context)
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{
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OpCodeSystem op = (OpCodeSystem)context.CurrOp;
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Operand vSh = context.ShiftLeft(GetFlag(PState.VFlag), Const((int)PState.VFlag));
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Operand cSh = context.ShiftLeft(GetFlag(PState.CFlag), Const((int)PState.CFlag));
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Operand zSh = context.ShiftLeft(GetFlag(PState.ZFlag), Const((int)PState.ZFlag));
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Operand nSh = context.ShiftLeft(GetFlag(PState.NFlag), Const((int)PState.NFlag));
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Operand nzcvSh = context.BitwiseOr(context.BitwiseOr(nSh, zSh), context.BitwiseOr(cSh, vSh));
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SetIntOrZR(context, op.Rt, nzcvSh);
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}
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private static void EmitSetNzcv(ArmEmitterContext context)
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{
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OpCodeSystem op = (OpCodeSystem)context.CurrOp;
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Operand t = GetIntOrZR(context, op.Rt);
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t = context.ConvertI64ToI32(t);
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Operand v = context.ShiftRightUI(t, Const((int)PState.VFlag));
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v = context.BitwiseAnd (v, Const(1));
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Operand c = context.ShiftRightUI(t, Const((int)PState.CFlag));
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c = context.BitwiseAnd (c, Const(1));
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Operand z = context.ShiftRightUI(t, Const((int)PState.ZFlag));
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z = context.BitwiseAnd (z, Const(1));
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Operand n = context.ShiftRightUI(t, Const((int)PState.NFlag));
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n = context.BitwiseAnd (n, Const(1));
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SetFlag(context, PState.VFlag, v);
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SetFlag(context, PState.CFlag, c);
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SetFlag(context, PState.ZFlag, z);
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SetFlag(context, PState.NFlag, n);
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}
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}
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}
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