mirror of
https://github.com/Ryujinx/Ryujinx.git
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b2b736abc2
* Fix typos * Remove unneeded using statements * Enforce var style more * Remove redundant qualifiers * Fix some indentation * Disable naming warnings on files with external enum names * Fix build * Mass find & replace for comments with no spacing * Standardize todo capitalization and for/if spacing
350 lines
No EOL
12 KiB
C#
350 lines
No EOL
12 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.IntermediateRepresentation;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Threading;
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using static ChocolArm64.Instructions.InstEmitMemoryHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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[Flags]
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private enum AccessType
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{
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None = 0,
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Ordered = 1,
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Exclusive = 2,
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OrderedEx = Ordered | Exclusive
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}
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public static void Clrex(ILEmitterCtx context)
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{
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitPrivateCall(typeof(CpuThreadState), nameof(CpuThreadState.ClearExclusiveAddress));
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}
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public static void Dmb(ILEmitterCtx context) => EmitBarrier(context);
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public static void Dsb(ILEmitterCtx context) => EmitBarrier(context);
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public static void Ldar(ILEmitterCtx context) => EmitLdr(context, AccessType.Ordered);
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public static void Ldaxr(ILEmitterCtx context) => EmitLdr(context, AccessType.OrderedEx);
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public static void Ldxr(ILEmitterCtx context) => EmitLdr(context, AccessType.Exclusive);
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public static void Ldxp(ILEmitterCtx context) => EmitLdp(context, AccessType.Exclusive);
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public static void Ldaxp(ILEmitterCtx context) => EmitLdp(context, AccessType.OrderedEx);
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private static void EmitLdr(ILEmitterCtx context, AccessType accType)
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{
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EmitLoad(context, accType, pair: false);
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}
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private static void EmitLdp(ILEmitterCtx context, AccessType accType)
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{
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EmitLoad(context, accType, pair: true);
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}
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private static void EmitLoad(ILEmitterCtx context, AccessType accType, bool pair)
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{
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OpCodeMemEx64 op = (OpCodeMemEx64)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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context.EmitLdint(op.Rn);
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context.EmitSttmp();
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if (exclusive)
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{
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdtmp();
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context.EmitPrivateCall(typeof(CpuThreadState), nameof(CpuThreadState.SetExclusiveAddress));
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}
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void WriteExclusiveValue(string propName)
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{
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context.Emit(OpCodes.Dup);
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if (op.Size < 3)
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{
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context.Emit(OpCodes.Conv_U8);
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}
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context.EmitSttmp2();
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdtmp2();
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context.EmitCallPrivatePropSet(typeof(CpuThreadState), propName);
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}
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if (pair)
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{
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// Exclusive loads should be atomic. For pairwise loads, we need to
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// read all the data at once. For a 32-bits pairwise load, we do a
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// simple 64-bits load, for a 128-bits load, we need to call a special
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// method to read 128-bits atomically.
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if (op.Size == 2)
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{
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context.EmitLdtmp();
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EmitReadZxCall(context, 3);
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context.Emit(OpCodes.Dup);
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// Mask low half.
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context.Emit(OpCodes.Conv_U4);
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if (exclusive)
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{
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WriteExclusiveValue(nameof(CpuThreadState.ExclusiveValueLow));
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}
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context.EmitStintzr(op.Rt);
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// Shift high half.
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context.EmitLsr(32);
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context.Emit(OpCodes.Conv_U4);
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if (exclusive)
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{
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WriteExclusiveValue(nameof(CpuThreadState.ExclusiveValueHigh));
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}
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context.EmitStintzr(op.Rt2);
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}
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else if (op.Size == 3)
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{
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdtmp();
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context.EmitPrivateCall(typeof(MemoryManager), nameof(MemoryManager.AtomicReadInt128));
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context.Emit(OpCodes.Dup);
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// Load low part of the vector.
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context.EmitLdc_I4(0);
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context.EmitLdc_I4(3);
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorExtractIntZx));
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if (exclusive)
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{
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WriteExclusiveValue(nameof(CpuThreadState.ExclusiveValueLow));
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}
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context.EmitStintzr(op.Rt);
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// Load high part of the vector.
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context.EmitLdc_I4(1);
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context.EmitLdc_I4(3);
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VectorHelper.EmitCall(context, nameof(VectorHelper.VectorExtractIntZx));
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if (exclusive)
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{
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WriteExclusiveValue(nameof(CpuThreadState.ExclusiveValueHigh));
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}
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context.EmitStintzr(op.Rt2);
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}
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else
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{
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throw new InvalidOperationException($"Invalid load size of {1 << op.Size} bytes.");
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}
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}
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else
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{
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// 8, 16, 32 or 64-bits (non-pairwise) load.
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context.EmitLdtmp();
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EmitReadZxCall(context, op.Size);
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if (exclusive)
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{
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WriteExclusiveValue(nameof(CpuThreadState.ExclusiveValueLow));
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}
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context.EmitStintzr(op.Rt);
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}
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}
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public static void Pfrm(ILEmitterCtx context)
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{
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// Memory Prefetch, execute as no-op.
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}
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public static void Stlr(ILEmitterCtx context) => EmitStr(context, AccessType.Ordered);
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public static void Stlxr(ILEmitterCtx context) => EmitStr(context, AccessType.OrderedEx);
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public static void Stxr(ILEmitterCtx context) => EmitStr(context, AccessType.Exclusive);
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public static void Stxp(ILEmitterCtx context) => EmitStp(context, AccessType.Exclusive);
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public static void Stlxp(ILEmitterCtx context) => EmitStp(context, AccessType.OrderedEx);
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private static void EmitStr(ILEmitterCtx context, AccessType accType)
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{
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EmitStore(context, accType, pair: false);
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}
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private static void EmitStp(ILEmitterCtx context, AccessType accType)
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{
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EmitStore(context, accType, pair: true);
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}
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private static void EmitStore(ILEmitterCtx context, AccessType accType, bool pair)
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{
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OpCodeMemEx64 op = (OpCodeMemEx64)context.CurrOp;
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bool ordered = (accType & AccessType.Ordered) != 0;
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bool exclusive = (accType & AccessType.Exclusive) != 0;
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if (ordered)
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{
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EmitBarrier(context);
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}
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if (exclusive)
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{
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ILLabel lblEx = new ILLabel();
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ILLabel lblEnd = new ILLabel();
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitLdint(op.Rn);
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context.EmitPrivateCall(typeof(CpuThreadState), nameof(CpuThreadState.CheckExclusiveAddress));
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context.Emit(OpCodes.Brtrue_S, lblEx);
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// Address check failed, set error right away and do not store anything.
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context.EmitLdc_I4(1);
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context.EmitStintzr(op.Rs);
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context.Emit(OpCodes.Br, lblEnd);
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// Address check passed.
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context.MarkLabel(lblEx);
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context.EmitLdarg(TranslatedSub.MemoryArgIdx);
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context.EmitLdint(op.Rn);
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitCallPrivatePropGet(typeof(CpuThreadState), nameof(CpuThreadState.ExclusiveValueLow));
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void EmitCast()
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{
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// The input should be always int64.
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switch (op.Size)
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{
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case 0: context.Emit(OpCodes.Conv_U1); break;
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case 1: context.Emit(OpCodes.Conv_U2); break;
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case 2: context.Emit(OpCodes.Conv_U4); break;
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}
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}
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EmitCast();
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if (pair)
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{
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context.EmitLdarg(TranslatedSub.StateArgIdx);
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context.EmitCallPrivatePropGet(typeof(CpuThreadState), nameof(CpuThreadState.ExclusiveValueHigh));
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EmitCast();
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context.EmitLdintzr(op.Rt);
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EmitCast();
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context.EmitLdintzr(op.Rt2);
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EmitCast();
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switch (op.Size)
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{
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case 2: context.EmitPrivateCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchange2xInt32)); break;
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case 3: context.EmitPrivateCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchangeInt128)); break;
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default: throw new InvalidOperationException($"Invalid store size of {1 << op.Size} bytes.");
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}
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}
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else
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{
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context.EmitLdintzr(op.Rt);
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EmitCast();
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switch (op.Size)
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{
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case 0: context.EmitCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchangeByte)); break;
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case 1: context.EmitCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchangeInt16)); break;
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case 2: context.EmitCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchangeInt32)); break;
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case 3: context.EmitCall(typeof(MemoryManager), nameof(MemoryManager.AtomicCompareExchangeInt64)); break;
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default: throw new InvalidOperationException($"Invalid store size of {1 << op.Size} bytes.");
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}
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}
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// The value returned is a bool, true if the values compared
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// were equal and the new value was written, false otherwise.
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// We need to invert this result, as on ARM 1 indicates failure,
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// and 0 success on those instructions.
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Conv_U8);
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context.EmitStintzr(op.Rs);
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// Only clear the exclusive monitor if the store was successful (Rs = false).
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context.Emit(OpCodes.Brtrue_S, lblEnd);
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Clrex(context);
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context.MarkLabel(lblEnd);
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}
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else
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{
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void EmitWriteCall(int rt, long offset)
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{
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context.EmitLdint(op.Rn);
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if (offset != 0)
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{
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context.EmitLdc_I8(offset);
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context.Emit(OpCodes.Add);
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}
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context.EmitLdintzr(rt);
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InstEmitMemoryHelper.EmitWriteCall(context, op.Size);
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}
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EmitWriteCall(op.Rt, 0);
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if (pair)
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{
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EmitWriteCall(op.Rt2, 1 << op.Size);
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}
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}
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}
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private static void EmitBarrier(ILEmitterCtx context)
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{
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// Note: This barrier is most likely not necessary, and probably
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// doesn't make any difference since we need to do a ton of stuff
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// (software MMU emulation) to read or write anything anyway.
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context.EmitCall(typeof(Thread), nameof(Thread.MemoryBarrier));
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}
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}
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} |