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Ryujinx/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code ()
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

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9.3 KiB
C#

using Ryujinx.Tests.Unicorn.Native;
using System;
namespace Ryujinx.Tests.Unicorn
{
public class UnicornAArch64
{
internal readonly IntPtr uc;
public IndexedProperty<int, ulong> X
{
get
{
return new IndexedProperty<int, ulong>(
(int i) => GetX(i),
(int i, ulong value) => SetX(i, value));
}
}
public IndexedProperty<int, SimdValue> Q
{
get
{
return new IndexedProperty<int, SimdValue>(
(int i) => GetQ(i),
(int i, SimdValue value) => SetQ(i, value));
}
}
public ulong LR
{
get => GetRegister(ArmRegister.LR);
set => SetRegister(ArmRegister.LR, value);
}
public ulong SP
{
get => GetRegister(ArmRegister.SP);
set => SetRegister(ArmRegister.SP, value);
}
public ulong PC
{
get => GetRegister(ArmRegister.PC);
set => SetRegister(ArmRegister.PC, value);
}
public uint Pstate
{
get => (uint)GetRegister(ArmRegister.PSTATE);
set => SetRegister(ArmRegister.PSTATE, (uint)value);
}
public int Fpcr
{
get => (int)GetRegister(ArmRegister.FPCR);
set => SetRegister(ArmRegister.FPCR, (uint)value);
}
public int Fpsr
{
get => (int)GetRegister(ArmRegister.FPSR);
set => SetRegister(ArmRegister.FPSR, (uint)value);
}
public bool OverflowFlag
{
get => (Pstate & 0x10000000u) != 0;
set => Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u);
}
public bool CarryFlag
{
get => (Pstate & 0x20000000u) != 0;
set => Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u);
}
public bool ZeroFlag
{
get => (Pstate & 0x40000000u) != 0;
set => Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u);
}
public bool NegativeFlag
{
get => (Pstate & 0x80000000u) != 0;
set => Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u);
}
public UnicornAArch64()
{
Interface.Checked(Interface.uc_open(UnicornArch.UC_ARCH_ARM64, UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
SetRegister(ArmRegister.CPACR_EL1, 0x00300000);
}
~UnicornAArch64()
{
Interface.Checked(Native.Interface.uc_close(uc));
}
public void RunForCount(ulong count)
{
Interface.Checked(Native.Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
}
public void Step()
{
RunForCount(1);
}
private static ArmRegister[] XRegisters = new ArmRegister[31]
{
ArmRegister.X0,
ArmRegister.X1,
ArmRegister.X2,
ArmRegister.X3,
ArmRegister.X4,
ArmRegister.X5,
ArmRegister.X6,
ArmRegister.X7,
ArmRegister.X8,
ArmRegister.X9,
ArmRegister.X10,
ArmRegister.X11,
ArmRegister.X12,
ArmRegister.X13,
ArmRegister.X14,
ArmRegister.X15,
ArmRegister.X16,
ArmRegister.X17,
ArmRegister.X18,
ArmRegister.X19,
ArmRegister.X20,
ArmRegister.X21,
ArmRegister.X22,
ArmRegister.X23,
ArmRegister.X24,
ArmRegister.X25,
ArmRegister.X26,
ArmRegister.X27,
ArmRegister.X28,
ArmRegister.X29,
ArmRegister.X30,
};
private static ArmRegister[] QRegisters = new ArmRegister[32]
{
ArmRegister.Q0,
ArmRegister.Q1,
ArmRegister.Q2,
ArmRegister.Q3,
ArmRegister.Q4,
ArmRegister.Q5,
ArmRegister.Q6,
ArmRegister.Q7,
ArmRegister.Q8,
ArmRegister.Q9,
ArmRegister.Q10,
ArmRegister.Q11,
ArmRegister.Q12,
ArmRegister.Q13,
ArmRegister.Q14,
ArmRegister.Q15,
ArmRegister.Q16,
ArmRegister.Q17,
ArmRegister.Q18,
ArmRegister.Q19,
ArmRegister.Q20,
ArmRegister.Q21,
ArmRegister.Q22,
ArmRegister.Q23,
ArmRegister.Q24,
ArmRegister.Q25,
ArmRegister.Q26,
ArmRegister.Q27,
ArmRegister.Q28,
ArmRegister.Q29,
ArmRegister.Q30,
ArmRegister.Q31,
};
public ulong GetX(int index)
{
if ((uint)index > 30)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
return GetRegister(XRegisters[index]);
}
public void SetX(int index, ulong value)
{
if ((uint)index > 30)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
SetRegister(XRegisters[index], value);
}
public SimdValue GetQ(int index)
{
if ((uint)index > 31)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
return GetVector(QRegisters[index]);
}
public void SetQ(int index, SimdValue value)
{
if ((uint)index > 31)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
SetVector(QRegisters[index], value);
}
private ulong GetRegister(ArmRegister register)
{
byte[] data = new byte[8];
Interface.Checked(Native.Interface.uc_reg_read(uc, (int)register, data));
return (ulong)BitConverter.ToInt64(data, 0);
}
private void SetRegister(ArmRegister register, ulong value)
{
byte[] data = BitConverter.GetBytes(value);
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
}
private SimdValue GetVector(ArmRegister register)
{
byte[] data = new byte[16];
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
return new SimdValue(data);
}
private void SetVector(ArmRegister register, SimdValue value)
{
byte[] data = value.ToArray();
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
}
public byte[] MemoryRead(ulong address, ulong size)
{
byte[] value = new byte[size];
Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
return value;
}
public byte MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
public void MemoryWrite(ulong address, byte[] value)
{
Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
}
public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new byte[]{value});
public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
{
Interface.Checked(Interface.uc_mem_map(uc, address, size, (uint)permissions));
}
public void MemoryUnmap(ulong address, ulong size)
{
Interface.Checked(Interface.uc_mem_unmap(uc, address, size));
}
public void MemoryProtect(ulong address, ulong size, MemoryPermission permissions)
{
Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
}
public static bool IsAvailable()
{
try
{
Interface.uc_version(out _, out _);
return true;
}
catch (DllNotFoundException)
{
return false;
}
}
}
}