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56a61a5758
Ryujinx
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Ryujinx.Tests
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Cpu
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LDj3SNuD
56a61a5758
CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (
#1394
)
...
* Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. * Update Ptc.cs
2020-07-17 10:57:49 -03:00
..
CpuTest.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (
#1335
)
2020-07-13 21:08:47 +10:00
CpuTest32.cs
CpuTestAlu.cs
CpuTestAlu32.cs
CpuTestAluBinary.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (
#1328
)
2020-07-13 20:48:14 +10:00
CpuTestAluBinary32.cs
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (
#1328
)
2020-07-13 20:48:14 +10:00
CpuTestAluImm.cs
CpuTestAluRs.cs
Add a new JIT compiler for CPU code (
#693
)
2019-08-08 21:56:22 +03:00
CpuTestAluRs32.cs
CpuTestAluRx.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (
#489
)
2018-11-01 01:22:09 -03:00
CpuTestBf32.cs
CpuTestBfm.cs
CpuTestCcmpImm.cs
CpuTestCcmpReg.cs
CpuTestCsel.cs
CpuTestMisc.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (
#1335
)
2020-07-13 21:08:47 +10:00
CpuTestMov.cs
CpuTestMul.cs
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (
#489
)
2018-11-01 01:22:09 -03:00
CpuTestMul32.cs
CpuTestSimd.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (
#1335
)
2020-07-13 21:08:47 +10:00
CpuTestSimd32.cs
CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (
#1394
)
2020-07-17 10:57:49 -03:00
CpuTestSimdCrypto.cs
CpuTestSimdCrypto32.cs
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (
#982
)
2020-03-14 10:29:58 +11:00
CpuTestSimdCvt.cs
Implemented fast paths for: (
#846
)
2019-12-29 22:22:47 -03:00
CpuTestSimdExt.cs
Add a new JIT compiler for CPU code (
#693
)
2019-08-08 21:56:22 +03:00
CpuTestSimdFcond.cs
CpuTestSimdFmov.cs
CpuTestSimdImm.cs
CpuTestSimdIns.cs
CpuTestSimdLogical32.cs
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (
#982
)
2020-03-14 10:29:58 +11:00
CpuTestSimdMemory32.cs
CpuTestSimdMov32.cs
CpuTestSimdReg.cs
Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (
#1335
)
2020-07-13 21:08:47 +10:00
CpuTestSimdReg32.cs
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (
#1390
)
2020-07-17 14:21:40 +10:00
CpuTestSimdRegElem.cs
CpuTestSimdRegElem32.cs
CpuTestSimdRegElemF.cs
CpuTestSimdShImm.cs
CpuTestSimdShImm32.cs
CpuTestSimdTbl.cs
CpuTestSystem.cs