mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-03 14:12:01 +00:00
352 lines
12 KiB
C#
352 lines
12 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.Instructions.InstEmitMemoryHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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namespace ARMeilleure.Instructions
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{
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static partial class InstEmit32
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{
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public static void Vld1(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 1, true);
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}
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public static void Vld2(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 2, true);
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}
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public static void Vld3(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 3, true);
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}
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public static void Vld4(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 4, true);
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}
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public static void Vst1(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 1, false);
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}
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public static void Vst2(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 2, false);
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}
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public static void Vst3(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 3, false);
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}
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public static void Vst4(ArmEmitterContext context)
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{
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EmitVStoreOrLoadN(context, 4, false);
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}
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public static void EmitVStoreOrLoadN(ArmEmitterContext context, int count, bool load)
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{
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if (context.CurrOp is OpCode32SimdMemSingle)
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{
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OpCode32SimdMemSingle op = (OpCode32SimdMemSingle)context.CurrOp;
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int eBytes = 1 << op.Size;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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// TODO: Check alignment.
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int offset = 0;
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int d = op.Vd;
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for (int i = 0; i < count; i++)
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{
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// Write an element from a double simd register.
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Operand address = context.Add(n, Const(offset));
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if (eBytes == 8)
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{
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if (load)
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{
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EmitDVectorLoad(context, address, d);
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}
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else
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{
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EmitDVectorStore(context, address, d);
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}
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}
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else
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{
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int index = ((d & 1) << (3 - op.Size)) + op.Index;
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if (load)
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{
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if (op.Replicate)
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{
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var regs = (count > 1) ? 1 : op.Increment;
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for (int reg = 0; reg < regs; reg++)
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{
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int dreg = reg + d;
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int rIndex = ((dreg & 1) << (3 - op.Size));
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int limit = rIndex + (1 << (3 - op.Size));
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while (rIndex < limit)
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{
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EmitLoadSimd(context, address, GetVecA32(dreg >> 1), dreg >> 1, rIndex++, op.Size);
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}
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}
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}
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else
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{
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EmitLoadSimd(context, address, GetVecA32(d >> 1), d >> 1, index, op.Size);
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}
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}
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else
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{
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EmitStoreSimd(context, address, d >> 1, index, op.Size);
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}
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}
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offset += eBytes;
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d += op.Increment;
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}
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if (op.WBack)
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{
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if (op.RegisterIndex)
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{
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Operand m = GetIntA32(context, op.Rm);
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SetIntA32(context, op.Rn, context.Add(n, m));
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}
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else
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(count * eBytes)));
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}
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}
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}
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else
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{
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OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;
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int eBytes = 1 << op.Size;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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int offset = 0;
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int d = op.Vd;
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for (int reg = 0; reg < op.Regs; reg++)
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{
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for (int elem = 0; elem < op.Elems; elem++)
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{
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int elemD = d + reg;
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for (int i = 0; i < count; i++)
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{
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// Write an element from a double simd register
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// add ebytes for each element.
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Operand address = context.Add(n, Const(offset));
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int index = ((elemD & 1) << (3 - op.Size)) + elem;
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if (eBytes == 8)
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{
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if (load)
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{
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EmitDVectorLoad(context, address, elemD);
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}
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else
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{
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EmitDVectorStore(context, address, elemD);
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}
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}
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else
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{
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if (load)
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{
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EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
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}
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else
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{
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EmitStoreSimd(context, address, elemD >> 1, index, op.Size);
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}
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}
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offset += eBytes;
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elemD += op.Increment;
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}
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}
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}
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if (op.WBack)
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{
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if (op.RegisterIndex)
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{
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Operand m = GetIntA32(context, op.Rm);
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SetIntA32(context, op.Rn, context.Add(n, m));
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}
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else
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(count * 8 * op.Regs)));
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}
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}
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}
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}
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public static void Vldm(ArmEmitterContext context)
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{
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OpCode32SimdMemMult op = (OpCode32SimdMemMult)context.CurrOp;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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Operand baseAddress = context.Add(n, Const(op.Offset));
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bool writeBack = op.PostOffset != 0;
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if (writeBack)
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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int range = op.RegisterRange;
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int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd;
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int offset = 0;
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int byteSize = 4;
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for (int num = 0; num < range; num++, sReg++)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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Operand vec = GetVecA32(sReg >> 2);
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EmitLoadSimd(context, address, vec, sReg >> 2, sReg & 3, WordSizeLog2);
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offset += byteSize;
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}
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}
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public static void Vstm(ArmEmitterContext context)
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{
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OpCode32SimdMemMult op = (OpCode32SimdMemMult)context.CurrOp;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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Operand baseAddress = context.Add(n, Const(op.Offset));
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bool writeBack = op.PostOffset != 0;
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if (writeBack)
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{
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SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset)));
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}
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int offset = 0;
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int range = op.RegisterRange;
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int sReg = (op.DoubleWidth) ? (op.Vd << 1) : op.Vd;
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int byteSize = 4;
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for (int num = 0; num < range; num++, sReg++)
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{
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Operand address = context.Add(baseAddress, Const(offset));
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EmitStoreSimd(context, address, sReg >> 2, sReg & 3, WordSizeLog2);
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offset += byteSize;
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}
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}
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public static void Vldr(ArmEmitterContext context)
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{
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EmitVLoadOrStore(context, AccessType.Load);
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}
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public static void Vstr(ArmEmitterContext context)
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{
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EmitVLoadOrStore(context, AccessType.Store);
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}
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private static void EmitDVectorStore(ArmEmitterContext context, Operand address, int vecD)
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{
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int vecQ = vecD >> 1;
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int vecSElem = (vecD & 1) << 1;
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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EmitStoreSimd(context, address, vecQ, vecSElem, WordSizeLog2);
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EmitStoreSimd(context, context.Add(address, Const(4)), vecQ, vecSElem | 1, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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EmitStoreSimd(context, address, vecQ, vecSElem | 1, WordSizeLog2);
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EmitStoreSimd(context, context.Add(address, Const(4)), vecQ, vecSElem, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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private static void EmitDVectorLoad(ArmEmitterContext context, Operand address, int vecD)
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{
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int vecQ = vecD >> 1;
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int vecSElem = (vecD & 1) << 1;
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Operand vec = GetVecA32(vecQ);
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Operand lblBigEndian = Label();
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Operand lblEnd = Label();
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context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
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EmitLoadSimd(context, address, vec, vecQ, vecSElem, WordSizeLog2);
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EmitLoadSimd(context, context.Add(address, Const(4)), vec, vecQ, vecSElem | 1, WordSizeLog2);
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context.Branch(lblEnd);
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context.MarkLabel(lblBigEndian);
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EmitLoadSimd(context, address, vec, vecQ, vecSElem | 1, WordSizeLog2);
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EmitLoadSimd(context, context.Add(address, Const(4)), vec, vecQ, vecSElem, WordSizeLog2);
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context.MarkLabel(lblEnd);
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}
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private static void EmitVLoadOrStore(ArmEmitterContext context, AccessType accType)
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{
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OpCode32SimdMemImm op = (OpCode32SimdMemImm)context.CurrOp;
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Operand n = context.Copy(GetIntA32(context, op.Rn));
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Operand m = GetMemM(context, setCarry: false);
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Operand address = op.Add
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? context.Add(n, m)
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: context.Subtract(n, m);
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int size = op.Size;
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if ((accType & AccessType.Load) != 0)
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{
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if (size == DWordSizeLog2)
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{
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EmitDVectorLoad(context, address, op.Vd);
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}
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else
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{
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Operand vec = GetVecA32(op.Vd >> 2);
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EmitLoadSimd(context, address, vec, op.Vd >> 2, (op.Vd & 3) << (2 - size), size);
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}
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}
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else
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{
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if (size == DWordSizeLog2)
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{
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EmitDVectorStore(context, address, op.Vd);
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}
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else
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{
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EmitStoreSimd(context, address, op.Vd >> 2, (op.Vd & 3) << (2 - size), size);
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}
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}
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}
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}
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}
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