mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-24 01:02:04 +00:00
36e8e074c9
* Fix and simplify TranslatorCache * Fix some assignment alignments, remove some unused usings * Changes to ILEmitter, separate it from ILEmitterCtx * Rename ILEmitter to ILMethodBuilder * Rename LdrLit and *_Fix opcodes * Revert TranslatorCache impl to the more performant one, fix a few issues with it * Allow EmitOpCode to be called even after everything has been emitted * Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point * Remove unneeded temp use * Add missing exit call on TestExclusive * Use better hash * Implement the == and != operators
100 lines
No EOL
3.1 KiB
C#
100 lines
No EOL
3.1 KiB
C#
using ChocolArm64.Instructions;
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namespace ChocolArm64.Decoders
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{
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class OpCodeSimdImm64 : OpCode64, IOpCodeSimd64
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{
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public int Rd { get; private set; }
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public long Imm { get; private set; }
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public int Size { get; private set; }
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public OpCodeSimdImm64(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Rd = opCode & 0x1f;
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int cMode = (opCode >> 12) & 0xf;
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int op = (opCode >> 29) & 0x1;
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int modeLow = cMode & 1;
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int modeHigh = cMode >> 1;
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long imm;
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imm = ((uint)opCode >> 5) & 0x1f;
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imm |= ((uint)opCode >> 11) & 0xe0;
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if (modeHigh == 0b111)
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{
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Size = modeLow != 0 ? op : 3;
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switch (op | (modeLow << 1))
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{
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case 0:
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//64-bits Immediate.
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//Transform abcd efgh into abcd efgh abcd efgh ...
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imm = (long)((ulong)imm * 0x0101010101010101);
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break;
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case 1:
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//64-bits Immediate.
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//Transform abcd efgh into aaaa aaaa bbbb bbbb ...
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imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
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imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
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imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
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imm = (long)((ulong)imm * 0x8040201008040201);
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imm = (long)((ulong)imm & 0x8080808080808080);
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imm |= imm >> 4;
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imm |= imm >> 2;
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imm |= imm >> 1;
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break;
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case 2:
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case 3:
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//Floating point Immediate.
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imm = DecoderHelper.DecodeImm8Float(imm, Size);
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break;
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}
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}
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else if ((modeHigh & 0b110) == 0b100)
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{
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//16-bits shifted Immediate.
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Size = 1; imm <<= (modeHigh & 1) << 3;
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}
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else if ((modeHigh & 0b100) == 0b000)
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{
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//32-bits shifted Immediate.
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Size = 2; imm <<= modeHigh << 3;
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}
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else if ((modeHigh & 0b111) == 0b110)
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{
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//32-bits shifted Immediate (fill with ones).
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Size = 2; imm = ShlOnes(imm, 8 << modeLow);
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}
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else
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{
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//8 bits without shift.
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Size = 0;
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}
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Imm = imm;
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RegisterSize = ((opCode >> 30) & 1) != 0
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? State.RegisterSize.Simd128
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: State.RegisterSize.Simd64;
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}
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private static long ShlOnes(long value, int shift)
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{
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if (shift != 0)
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{
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return value << shift | (long)(ulong.MaxValue >> (64 - shift));
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}
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else
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{
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return value;
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}
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}
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}
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} |