merry 7b35ebc64a T32: Implement ALU (shifted register) instructions (#3135) ... * T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2		2022-02-22 19:11:28 -03:00
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CodeGen	Add a limit on the number of uses a constant may have (#3097)	2022-02-09 17:42:47 -03:00
Common	Optimize LSRA (#2563)	2021-10-08 18:15:44 -03:00
Decoders	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
Diagnostics	Add an early TailMerge pass (#2721)	2021-10-18 19:51:22 -03:00
Instructions	T32: Implement ALU (shifted register) instructions (#3135)	2022-02-22 19:11:28 -03:00
IntermediateRepresentation	Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)	2022-01-21 12:47:34 -03:00
Memory	Replace CacheResourceWrite with more general "precise" write (#2684)	2021-09-29 02:27:03 +02:00
Signal	Remove usage of Mono.Posix.NETStandard accross all projects (#2906)	2021-12-08 18:24:26 -03:00
State	Implement a "Pause Emulation" option & hotkey (#2428)	2021-09-11 22:08:25 +02:00
Translation	ARMeilleure: Implement single stepping (#3133)	2022-02-22 11:11:42 -03:00
Allocators.cs	Optimize LSRA (#2563)	2021-10-08 18:15:44 -03:00
ARMeilleure.csproj	Remove usage of Mono.Posix.NETStandard accross all projects (#2906)	2021-12-08 18:24:26 -03:00
Optimizations.cs
Statistics.cs