1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-01 01:22:03 +00:00
Ryujinx/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs
gdkchan a731ab3a2a Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 21:56:22 +03:00

145 lines
5.8 KiB
C#

// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
using ARMeilleure.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdCrypto : CpuTest
{
[Test, Description("AESD <Vd>.16B, <Vn>.16B")]
public void Aesd_V([Values(0u)] uint rd,
[Values(1u)] uint rn,
[Values(0x7B5B546573745665ul)] ulong valueH,
[Values(0x63746F725D53475Dul)] ulong valueL,
[Random(2)] ulong roundKeyH,
[Random(2)] ulong roundKeyL,
[Values(0x8DCAB9BC035006BCul)] ulong resultH,
[Values(0x8F57161E00CAFD8Dul)] ulong resultL)
{
uint opcode = 0x4E285800; // AESD V0.16B, V0.16B
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL));
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH));
});
CompareAgainstUnicorn();
}
[Test, Description("AESE <Vd>.16B, <Vn>.16B")]
public void Aese_V([Values(0u)] uint rd,
[Values(1u)] uint rn,
[Values(0x7B5B546573745665ul)] ulong valueH,
[Values(0x63746F725D53475Dul)] ulong valueL,
[Random(2)] ulong roundKeyH,
[Random(2)] ulong roundKeyL,
[Values(0x8F92A04DFBED204Dul)] ulong resultH,
[Values(0x4C39B1402192A84Cul)] ulong resultL)
{
uint opcode = 0x4E284800; // AESE V0.16B, V0.16B
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH);
V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH);
ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL));
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH));
});
CompareAgainstUnicorn();
}
[Test, Description("AESIMC <Vd>.16B, <Vn>.16B")]
public void Aesimc_V([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Values(0x8DCAB9DC035006BCul)] ulong valueH,
[Values(0x8F57161E00CAFD8Dul)] ulong valueL,
[Values(0xD635A667928B5EAEul)] ulong resultH,
[Values(0xEEC9CC3BC55F5777ul)] ulong resultL)
{
uint opcode = 0x4E287800; // AESIMC V0.16B, V0.16B
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
V128 v = MakeVectorE0E1(valueL, valueH);
ExecutionContext context = SingleOpcode(
opcode,
v0: rn == 0u ? v : default(V128),
v1: rn == 1u ? v : default(V128));
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
if (rn == 1u)
{
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL));
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH));
});
}
CompareAgainstUnicorn();
}
[Test, Description("AESMC <Vd>.16B, <Vn>.16B")]
public void Aesmc_V([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[Values(0x627A6F6644B109C8ul)] ulong valueH,
[Values(0x2B18330A81C3B3E5ul)] ulong valueL,
[Values(0x7B5B546573745665ul)] ulong resultH,
[Values(0x63746F725D53475Dul)] ulong resultL)
{
uint opcode = 0x4E286800; // AESMC V0.16B, V0.16B
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
V128 v = MakeVectorE0E1(valueL, valueH);
ExecutionContext context = SingleOpcode(
opcode,
v0: rn == 0u ? v : default(V128),
v1: rn == 1u ? v : default(V128));
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL));
Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH));
});
if (rn == 1u)
{
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL));
Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH));
});
}
CompareAgainstUnicorn();
}
}
}