mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-19 18:12:01 +00:00
a804db6eed
* Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d double zero sign handling. Allows better handling of NaNs. * Optimized EmitSse2VectorIsNaNOpF() for multiple uses per opF.
485 lines
17 KiB
C#
485 lines
17 KiB
C#
#define Misc
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using ARMeilleure.State;
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using NUnit.Framework;
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using System;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Misc")]
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public sealed class CpuTestMisc : CpuTest
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{
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#if Misc
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#region "ValueSource (Types)"
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private static IEnumerable<ulong> _1S_F_()
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{
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
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if (!NoZeros)
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{
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yield return 0x0000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!NoInfs)
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{
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yield return 0x00000000FF800000ul; // -Infinity
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yield return 0x000000007F800000ul; // +Infinity
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}
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if (!NoNaNs)
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{
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yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (grbg << 32) | rnd1;
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yield return (grbg << 32) | rnd2;
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}
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}
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#endregion
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private const int RndCnt = 2;
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private const int RndCntImm = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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#region "AluImm & Csel"
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[Test, Pairwise]
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public void Adds_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0xB100001F; // ADDS X31, X0, #0, LSL #0 -> CMN X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: xn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Adds_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmn = 0x3100001F; // ADDS W31, W0, #0, LSL #0 -> CMN W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: wn);
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Opcode(opCmn);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_64bit([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0xF100001F; // SUBS X31, X0, #0, LSL #0 -> CMP X0, #0, LSL #0
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uint opCset = 0x9A9F07E0; // CSINC X0, X31, X31, EQ -> CSET X0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: xn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Subs_Csinc_32bit([Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
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[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
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[Values(0b00u, 0b01u)] uint shift, // <LSL #0, LSL #12>
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[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
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0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
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0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
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0b1100u, 0b1101u)] uint cond) // GT, LE>
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{
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uint opCmp = 0x7100001F; // SUBS W31, W0, #0, LSL #0 -> CMP W0, #0, LSL #0
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uint opCset = 0x1A9F07E0; // CSINC W0, W31, W31, EQ -> CSET W0, NE
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opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
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opCset |= ((cond & 15) << 12);
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SetContext(x0: wn);
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Opcode(opCmp);
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Opcode(opCset);
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Opcode(0xD65F03C0); // RET
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ExecuteOpcodes();
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CompareAgainstUnicorn();
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}
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#endregion
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[Explicit]
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0x00000005u)]
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public void Misc1(uint a)
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{
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// ((a + 3) * (a - 5)) / ((a + 5) * (a - 3)) = 0
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/*
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ADD W2, W0, 3
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SUB W1, W0, #5
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MUL W2, W2, W1
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ADD W1, W0, 5
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SUB W0, W0, #3
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MUL W0, W1, W0
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SDIV W0, W2, W0
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RET
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*/
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SetContext(x0: a);
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Opcode(0x11000C02);
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Opcode(0x51001401);
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Opcode(0x1B017C42);
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Opcode(0x11001401);
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Opcode(0x51000C00);
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Opcode(0x1B007C20);
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Opcode(0x1AC00C40);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.Zero);
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}
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[Explicit]
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-12f, -6f)]
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[TestCase(-12f, 3f)]
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[TestCase( -8f, -8f)]
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[TestCase( -6f, -12f)]
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[TestCase( -5f, -20f)]
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[TestCase( -4f, 2f)]
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[TestCase( -3f, 12f)]
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[TestCase( -2f, 4f)]
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[TestCase( 2f, -4f)]
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[TestCase( 3f, -12f)]
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[TestCase( 4f, -2f)]
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[TestCase( 5f, 20f)]
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[TestCase( 6f, 12f)]
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[TestCase( 8f, 8f)]
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[TestCase( 12f, -3f)]
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[TestCase( 12f, 6f)]
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[TestCase( 20f, 5f)]
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public void Misc2(float a, float b)
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{
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// 1 / ((1 / a + 1 / b) ^ 2) = 16
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/*
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FMOV S2, 1.0e+0
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FDIV S0, S2, S0
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FDIV S1, S2, S1
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FADD S0, S0, S1
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FDIV S0, S2, S0
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FMUL S0, S0, S0
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RET
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*/
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SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
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Opcode(0x1E2E1002);
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Opcode(0x1E201840);
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Opcode(0x1E211841);
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Opcode(0x1E212800);
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Opcode(0x1E201840);
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Opcode(0x1E200800);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetV(0).As<float>(), Is.EqualTo(16f));
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}
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[Explicit]
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-12d, -6d)]
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[TestCase(-12d, 3d)]
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[TestCase( -8d, -8d)]
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[TestCase( -6d, -12d)]
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[TestCase( -5d, -20d)]
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[TestCase( -4d, 2d)]
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[TestCase( -3d, 12d)]
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[TestCase( -2d, 4d)]
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[TestCase( 2d, -4d)]
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[TestCase( 3d, -12d)]
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[TestCase( 4d, -2d)]
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[TestCase( 5d, 20d)]
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[TestCase( 6d, 12d)]
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[TestCase( 8d, 8d)]
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[TestCase( 12d, -3d)]
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[TestCase( 12d, 6d)]
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[TestCase( 20d, 5d)]
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public void Misc3(double a, double b)
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{
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// 1 / ((1 / a + 1 / b) ^ 2) = 16
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/*
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FMOV D2, 1.0e+0
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FDIV D0, D2, D0
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FDIV D1, D2, D1
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FADD D0, D0, D1
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FDIV D0, D2, D0
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FMUL D0, D0, D0
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RET
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*/
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SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
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Opcode(0x1E6E1002);
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Opcode(0x1E601840);
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Opcode(0x1E611841);
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Opcode(0x1E612800);
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Opcode(0x1E601840);
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Opcode(0x1E600800);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetV(0).As<double>(), Is.EqualTo(16d));
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}
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[Test, Ignore("The Tester supports only one return point.")]
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public void MiscF([Range(0u, 92u, 1u)] uint a)
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{
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ulong Fn(uint n)
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{
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ulong x = 0, y = 1, z;
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if (n == 0)
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{
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return x;
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}
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for (uint i = 2; i <= n; i++)
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{
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z = x + y;
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x = y;
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y = z;
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}
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return y;
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}
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/*
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0x0000000000001000: MOV W4, W0
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0x0000000000001004: CBZ W0, #0x34
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0x0000000000001008: CMP W0, #1
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0x000000000000100C: B.LS #0x34
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0x0000000000001010: MOVZ W2, #0x2
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0x0000000000001014: MOVZ X1, #0x1
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0x0000000000001018: MOVZ X3, #0
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0x000000000000101C: ADD X0, X3, X1
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0x0000000000001020: ADD W2, W2, #1
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0x0000000000001024: MOV X3, X1
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0x0000000000001028: MOV X1, X0
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0x000000000000102C: CMP W4, W2
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0x0000000000001030: B.HS #-0x14
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0x0000000000001034: RET
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0x0000000000001038: MOVZ X0, #0
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0x000000000000103C: RET
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0x0000000000001040: MOVZ X0, #0x1
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0x0000000000001044: RET
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*/
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SetContext(x0: a);
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Opcode(0x2A0003E4);
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Opcode(0x340001A0);
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Opcode(0x7100041F);
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Opcode(0x540001A9);
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Opcode(0x52800042);
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Opcode(0xD2800021);
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Opcode(0xD2800003);
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Opcode(0x8B010060);
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Opcode(0x11000442);
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Opcode(0xAA0103E3);
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Opcode(0xAA0003E1);
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Opcode(0x6B02009F);
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Opcode(0x54FFFF62);
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Opcode(0xD65F03C0);
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Opcode(0xD2800000);
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Opcode(0xD65F03C0);
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Opcode(0xD2800020);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(Fn(a)));
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}
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[Explicit]
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[Test]
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public void MiscR()
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{
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const ulong result = 5;
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/*
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0x0000000000001000: MOV X0, #2
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0x0000000000001004: MOV X1, #3
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0x0000000000001008: ADD X0, X0, X1
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0x000000000000100C: RET
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*/
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Opcode(0xD2800040);
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Opcode(0xD2800061);
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Opcode(0x8B010000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(result));
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Reset();
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/*
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0x0000000000001000: MOV X0, #3
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0x0000000000001004: MOV X1, #2
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0x0000000000001008: ADD X0, X0, X1
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0x000000000000100C: RET
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*/
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Opcode(0xD2800060);
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Opcode(0xD2800041);
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Opcode(0x8B010000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetContext().GetX(0), Is.EqualTo(result));
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}
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[Explicit]
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[TestCase( 0ul)]
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[TestCase( 1ul)]
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[TestCase( 2ul)]
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[TestCase(42ul)]
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public void SanityCheck(ulong a)
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{
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uint opcode = 0xD503201F; // NOP
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ExecutionContext context = SingleOpcode(opcode, x0: a);
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Assert.That(context.GetX(0), Is.EqualTo(a));
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}
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[Explicit]
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[Test, Pairwise]
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public void Misc4([ValueSource("_1S_F_")] ulong a,
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[ValueSource("_1S_F_")] ulong b,
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[ValueSource("_1S_F_")] ulong c,
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[Values(0ul, 1ul, 2ul, 3ul)] ulong displacement)
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{
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if (!BitConverter.IsLittleEndian)
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{
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Assert.Ignore();
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}
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for (ulong gapOffset = 0; gapOffset < displacement; gapOffset++)
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{
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SetWorkingMemory(gapOffset, TestContext.CurrentContext.Random.NextByte());
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}
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SetWorkingMemory(0x0 + displacement, BitConverter.GetBytes((uint)b));
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SetWorkingMemory(0x4 + displacement, BitConverter.GetBytes((uint)c));
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SetWorkingMemory(0x8 + displacement, TestContext.CurrentContext.Random.NextByte());
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SetWorkingMemory(0x9 + displacement, TestContext.CurrentContext.Random.NextByte());
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SetWorkingMemory(0xA + displacement, TestContext.CurrentContext.Random.NextByte());
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SetWorkingMemory(0xB + displacement, TestContext.CurrentContext.Random.NextByte());
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SetContext(
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x0: DataBaseAddress + displacement,
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v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()),
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v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
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v2: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
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overflow: TestContext.CurrentContext.Random.NextBool(),
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carry: TestContext.CurrentContext.Random.NextBool(),
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zero: TestContext.CurrentContext.Random.NextBool(),
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negative: TestContext.CurrentContext.Random.NextBool());
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Opcode(0xBD400001); // LDR S1, [X0,#0]
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Opcode(0xBD400402); // LDR S2, [X0,#4]
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Opcode(0x1E215801); // FMIN S1, S0, S1
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Opcode(0x1E222000); // FCMP S0, S2
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Opcode(0x1E214C40); // FCSEL S0, S2, S1, MI
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|
Opcode(0xBD000800); // STR S0, [X0,#8]
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|
Opcode(0xD65F03C0); // RET
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|
ExecuteOpcodes();
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
|
|
[Explicit]
|
|
[Test]
|
|
public void Misc5([ValueSource("_1S_F_")] ulong a)
|
|
{
|
|
SetContext(
|
|
v0: MakeVectorE0E1(a, TestContext.CurrentContext.Random.NextULong()),
|
|
v1: MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()),
|
|
overflow: TestContext.CurrentContext.Random.NextBool(),
|
|
carry: TestContext.CurrentContext.Random.NextBool(),
|
|
zero: TestContext.CurrentContext.Random.NextBool(),
|
|
negative: TestContext.CurrentContext.Random.NextBool());
|
|
|
|
Opcode(0x1E202008); // FCMP S0, #0.0
|
|
Opcode(0x1E2E1001); // FMOV S1, #1.0
|
|
Opcode(0x1E215800); // FMIN S0, S0, S1
|
|
Opcode(0x1E2703E1); // FMOV S1, WZR
|
|
Opcode(0x1E204C20); // FCSEL S0, S1, S0, MI
|
|
Opcode(0xD65F03C0); // RET
|
|
ExecuteOpcodes();
|
|
|
|
CompareAgainstUnicorn();
|
|
}
|
|
#endif
|
|
}
|
|
}
|