1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-04 17:52:01 +00:00
Ryujinx/ARMeilleure/IntermediateRepresentation
FICTURE7 8b3eba7e13
Reduce allocation during SSA construction (#2162)
* Reduce allocation during SSA construction

* Re-trigger CI
2021-04-02 19:26:16 +02:00
..
BasicBlock.cs
BasicBlockFrequency.cs
Comparison.cs
IIntrusiveListNode.cs
Instruction.cs
Intrinsic.cs
IntrinsicOperation.cs
IntrusiveList.cs
MemoryOperand.cs
Multiplier.cs
Node.cs
Operand.cs Reduce allocation during SSA construction (#2162) 2021-04-02 19:26:16 +02:00
OperandHelper.cs
OperandKind.cs
OperandType.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
Operation.cs
OperationHelper.cs
PhiNode.cs
Register.cs
RegisterType.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00