1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-13 20:42:03 +00:00
Ryujinx/ARMeilleure/Translation
merry 98e05ee4b7
ARMeilleure: Thumb support (All T16 instructions) (#3105)
* Decoders: Add InITBlock argument

* OpCodeTable: Minor cleanup

* OpCodeTable: Remove existing thumb instruction implementations

* OpCodeTable: Prepare for thumb instructions

* OpCodeTables: Improve thumb fast lookup

* Tests: Prepare for thumb tests

* T16: Implement BX

* T16: Implement LSL/LSR/ASR (imm)

* T16: Implement ADDS, SUBS (reg)

* T16: Implement ADDS, SUBS (3-bit immediate)

* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)

* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)

* T16: Implement ADD, CMP, MOV (high reg)

* T16: Implement BLX (reg)

* T16: Implement LDR (literal)

* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)

* T16: Implement {LDR,STR}{,B,H} (immediate)

* T16: Implement LDR/STR (SP)

* T16: Implement ADR

* T16: Implement Add to SP (immediate)

* T16: Implement ADD/SUB (SP)

* T16: Implement SXTH, SXTB, UXTH, UTXB

* T16: Implement CBZ, CBNZ

* T16: Implement PUSH, POP

* T16: Implement REV, REV16, REVSH

* T16: Implement NOP

* T16: Implement LDM, STM

* T16: Implement SVC

* T16: Implement B (conditional)

* T16: Implement B (unconditional)

* T16: Implement IT

* fixup! T16: Implement ADD/SUB (SP)

* fixup! T16: Implement Add to SP (immediate)

* fixup! T16: Implement IT

* CpuTestThumb: Add randomized tests

* Remove inITBlock argument

* Address nits

* Use index to handle IfThenBlockState

* Reduce line noise

* fixup

* nit
2022-02-17 19:39:45 -03:00
..
Cache misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
PTC Fix small precision error on CPU reciprocal estimate instructions (#3061) 2022-01-29 23:59:34 +01:00
ArmEmitterContext.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
Compiler.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
CompilerContext.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
DelegateHelper.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
DelegateInfo.cs PPTC Follow-up. (#1712) 2020-12-17 20:32:09 +01:00
Delegates.cs Add multi-level function table (#2228) 2021-05-29 18:06:28 -03:00
DispatcherFunction.cs Add multi-level function table (#2228) 2021-05-29 18:06:28 -03:00
Dominance.cs Replace LinkedList by IntrusiveList to avoid allocations on JIT (#931) 2020-02-17 22:30:54 +01:00
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
RegisterToLocal.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
RegisterUsage.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
RejitRequest.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
SsaConstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
SsaDeconstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
TranslatedFunction.cs Add inlined on translation call counting (#2190) 2021-04-18 23:43:53 +02:00
Translator.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
TranslatorStubs.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00