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CpuTest.cs
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Add multi-level function table (#2228)
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2021-05-29 18:06:28 -03:00 |
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CpuTest32.cs
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T32: Implement ALU (shifted register) instructions (#3135)
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2022-02-22 19:11:28 -03:00 |
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CpuTestAlu.cs
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Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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2019-06-12 09:03:31 -03:00 |
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CpuTestAlu32.cs
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ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)
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2022-02-08 10:46:42 +01:00 |
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CpuTestAluBinary.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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CpuTestAluBinary32.cs
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Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
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2020-07-13 20:48:14 +10:00 |
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CpuTestAluImm.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestAluImm32.cs
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A32: Fix ALU immediate instructions (#3179)
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2022-03-05 15:23:10 -03:00 |
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CpuTestAluRs.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestAluRs32.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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CpuTestAluRx.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestBf32.cs
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Add most of the A32 instruction set to ARMeilleure (#897)
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2020-02-24 08:20:40 +11:00 |
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CpuTestBfm.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestCcmpImm.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestCcmpReg.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestCsel.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestMisc.cs
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Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)
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2020-07-13 21:08:47 +10:00 |
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CpuTestMisc32.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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CpuTestMov.cs
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Implement a custom value generator for the Tests of the CLS and CLZ instructions (Base: 32, 64 bits. Simd: 8, 16, 32 bits). (#696)
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2019-06-12 09:03:31 -03:00 |
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CpuTestMul.cs
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Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
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2018-11-01 01:22:09 -03:00 |
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CpuTestMul32.cs
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Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
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2020-03-01 07:51:55 +11:00 |
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CpuTestSimd.cs
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CPU - Implement FCVTMS (Vector) (#2937)
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2022-01-04 16:45:28 -03:00 |
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CpuTestSimd32.cs
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Implement VCNT instruction (#1963)
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2021-02-22 16:26:13 +01:00 |
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CpuTestSimdCrypto.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdCrypto32.cs
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Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
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2020-03-14 10:29:58 +11:00 |
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CpuTestSimdCvt.cs
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Implement FCVTNS (Scalar GP) (#2953)
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2022-01-19 22:21:44 -03:00 |
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CpuTestSimdCvt32.cs
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Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
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2020-12-17 20:43:41 +01:00 |
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CpuTestSimdExt.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdFcond.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdFmov.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdImm.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdIns.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdLogical32.cs
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Implement VORN (register) Arm32 instruction (#2396)
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2021-06-23 23:21:23 +02:00 |
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CpuTestSimdMemory32.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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CpuTestSimdMov32.cs
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Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)
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2020-06-24 10:43:44 +10:00 |
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CpuTestSimdReg.cs
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CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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2021-01-04 23:45:54 +01:00 |
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CpuTestSimdReg32.cs
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CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
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2021-01-04 23:45:54 +01:00 |
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CpuTestSimdRegElem.cs
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Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
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2021-03-25 23:33:32 +01:00 |
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CpuTestSimdRegElem32.cs
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Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
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2020-03-11 11:49:27 +11:00 |
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CpuTestSimdRegElemF.cs
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Add a new JIT compiler for CPU code (#693)
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2019-08-08 21:56:22 +03:00 |
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CpuTestSimdShImm.cs
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CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)
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2020-08-31 20:48:21 -03:00 |
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CpuTestSimdShImm32.cs
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CPU: This PR fixes Fpscr, among other things. (#1433)
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2020-08-08 17:18:51 +02:00 |
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CpuTestSimdTbl.cs
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Add Tbx Inst. (fast & slow paths), with Tests. (#782)
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2019-10-04 11:43:20 -03:00 |
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CpuTestSystem.cs
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Add Mrs & Msr (Nzcv) Inst., with Tests. (#819)
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2019-11-14 13:08:07 +11:00 |
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CpuTestT32Alu.cs
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T32: Implement ALU (shifted register) instructions (#3135)
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2022-02-22 19:11:28 -03:00 |
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CpuTestT32Flow.cs
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T32: Implement B, B.cond, BL, BLX (#3155)
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2022-03-04 23:05:08 +01:00 |
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CpuTestThumb.cs
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T32: Implement ALU (shifted register) instructions (#3135)
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2022-02-22 19:11:28 -03:00 |
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PrecomputedThumbTestCase.cs
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T32: Implement ALU (shifted register) instructions (#3135)
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2022-02-22 19:11:28 -03:00 |
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