| .. |
|
ACryptoHelper.cs
|
Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
|
2018-08-20 01:20:26 -03:00 |
|
AInst.cs
|
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
2018-05-26 17:50:47 -03:00 |
|
AInstEmitAlu.cs
|
Remove broken adds/cmn with condition check optimization (#218)
|
2018-07-03 21:54:05 -03:00 |
|
AInstEmitAluHelper.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
|
AInstEmitBfm.cs
|
Fix corner cases of ADCS and SBFM
|
2018-02-26 15:56:34 -03:00 |
|
AInstEmitCcmp.cs
|
|
|
|
AInstEmitCsel.cs
|
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
|
2018-02-25 22:14:58 -03:00 |
|
AInstEmitException.cs
|
Implement SvcGetThreadContext3
|
2018-06-26 01:10:15 -03:00 |
|
AInstEmitFlow.cs
|
Remove cold methods from the CPU cache (#224)
|
2018-09-19 17:07:56 -03:00 |
|
AInstEmitHash.cs
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
|
2018-06-25 22:32:29 -03:00 |
|
AInstEmitMemory.cs
|
Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
|
2018-06-02 11:44:52 -03:00 |
|
AInstEmitMemoryEx.cs
|
Thread scheduler rewrite (#393)
|
2018-09-18 20:36:43 -03:00 |
|
AInstEmitMemoryHelper.cs
|
More flexible memory manager (#307)
|
2018-08-15 15:59:51 -03:00 |
|
AInstEmitMove.cs
|
|
|
|
AInstEmitMul.cs
|
|
|
|
AInstEmitSimdArithmetic.cs
|
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
|
2018-10-05 22:45:59 -03:00 |
|
AInstEmitSimdCmp.cs
|
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
2018-09-26 23:30:21 -03:00 |
|
AInstEmitSimdCrypto.cs
|
Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
|
2018-08-20 01:20:26 -03:00 |
|
AInstEmitSimdCvt.cs
|
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
2018-09-26 23:30:21 -03:00 |
|
AInstEmitSimdHash.cs
|
Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
|
2018-08-16 21:44:44 -03:00 |
|
AInstEmitSimdHelper.cs
|
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
|
2018-10-05 22:45:59 -03:00 |
|
AInstEmitSimdLogical.cs
|
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
2018-09-26 23:30:21 -03:00 |
|
AInstEmitSimdMemory.cs
|
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)
|
2018-07-14 13:13:02 -03:00 |
|
AInstEmitSimdMove.cs
|
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
2018-09-26 23:30:21 -03:00 |
|
AInstEmitSimdShift.cs
|
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
|
2018-09-17 01:54:05 -03:00 |
|
AInstEmitSystem.cs
|
Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
|
2018-03-13 21:24:32 -03:00 |
|
AInstEmitter.cs
|
|
|
|
AInstInterpreter.cs
|
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
|
2018-05-26 17:50:47 -03:00 |
|
ASoftFallback.cs
|
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
|
2018-09-08 14:24:29 -03:00 |
|
ASoftFloat.cs
|
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
|
2018-10-05 22:45:59 -03:00 |
|
AVectorHelper.cs
|
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)
|
2018-09-26 23:30:21 -03:00 |
bba9bf97d0