1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-12-21 01:22:02 +00:00
Ryujinx/ARMeilleure/Translation
merry b97ff4da5e
A32: Fix ALU immediate instructions (#3179)
* Tests: Add A32 tests for immediate ADC/ADCS/RSC/RSCS/SBC/SBCS

* A32: Fix bug in ADC/ADCS/RSC/RSCS/SBC/SBCS

* CpuTestAluImm32: Add more opcodes

* Increment PTC version
2022-03-05 15:23:10 -03:00
..
Cache misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
PTC A32: Fix ALU immediate instructions (#3179) 2022-03-05 15:23:10 -03:00
ArmEmitterContext.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
Compiler.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
CompilerContext.cs
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
DelegateHelper.cs
DelegateInfo.cs
Delegates.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
DispatcherFunction.cs
Dominance.cs
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs
IntervalTree.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
RegisterToLocal.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
RegisterUsage.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
RejitRequest.cs
SsaConstruction.cs Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145) 2022-02-22 10:32:10 -03:00
SsaDeconstruction.cs Reduce JIT GC allocations (#2515) 2021-08-17 15:08:34 -03:00
TranslatedFunction.cs
Translator.cs ARMeilleure: Implement single stepping (#3133) 2022-02-22 11:11:42 -03:00
TranslatorCache.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
TranslatorStubs.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00