mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-23 17:22:03 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
20 lines
No EOL
512 B
C#
20 lines
No EOL
512 B
C#
using ChocolArm64.Instructions;
|
|
|
|
namespace ChocolArm64.Decoders
|
|
{
|
|
class OpCode32Alu : OpCode32, IOpCode32Alu
|
|
{
|
|
public int Rd { get; private set; }
|
|
public int Rn { get; private set; }
|
|
|
|
public bool SetFlags { get; private set; }
|
|
|
|
public OpCode32Alu(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
|
{
|
|
Rd = (opCode >> 12) & 0xf;
|
|
Rn = (opCode >> 16) & 0xf;
|
|
|
|
SetFlags = ((opCode >> 20) & 1) != 0;
|
|
}
|
|
}
|
|
} |