mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-27 10:02:01 +00:00
c7387be0d2
* Update AOpCodeTable.cs * Update AInstEmitSimdShift.cs * Update CpuTestSimdShImm.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Create CpuTestSimdIns.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs
591 lines
18 KiB
C#
591 lines
18 KiB
C#
using ChocolArm64.Decoder;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using static ChocolArm64.Instruction.AInstEmitSimdHelper;
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namespace ChocolArm64.Instruction
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{
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static partial class AInstEmit
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{
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public static void Rshrn_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmNarrowOpZx(Context, Round: true);
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}
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public static void Shl_S(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitScalarUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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public static void Shl_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorUnaryOpZx(Context, () =>
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{
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Context.EmitLdc_I4(GetImmShl(Op));
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Context.Emit(OpCodes.Shl);
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});
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}
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public static void Shll_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Shift = 8 << Op.Size;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), Shift);
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}
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public static void Shrn_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmNarrowOpZx(Context, Round: false);
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}
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public static void Sli_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int Shift = GetImmShl(Op);
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ulong Mask = Shift != 0 ? ulong.MaxValue >> (64 - Shift) : 0;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shl);
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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Context.EmitLdc_I8((long)Mask);
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Context.Emit(OpCodes.And);
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Context.Emit(OpCodes.Or);
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EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Sqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqrshrn_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Sqrshrun_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqrshrun_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Sqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxSx);
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}
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public static void Sqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxSx);
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}
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public static void Sqshrun_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarSxZx);
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}
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public static void Sqshrun_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorSxZx);
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}
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public static void Srshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round);
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}
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public static void Srshr_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round);
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}
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public static void Srsra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Srsra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Sshl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: true);
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}
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public static void Sshll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinarySx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Sshr_S(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx);
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}
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public static void Sshr_V(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.VectorSx);
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}
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public static void Ssra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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public static void Ssra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
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}
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public static void Uqrshrn_S(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqrshrn_V(AILEmitterCtx Context)
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{
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EmitRoundShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Uqshrn_S(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.ScalarZxZx);
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}
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public static void Uqshrn_V(AILEmitterCtx Context)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.VectorZxZx);
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}
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public static void Urshr_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
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}
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public static void Urshr_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round);
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}
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public static void Ursra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ursra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
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}
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public static void Ushl_V(AILEmitterCtx Context)
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{
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EmitVectorShl(Context, Signed: false);
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}
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public static void Ushll_V(AILEmitterCtx Context)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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EmitVectorShImmWidenBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
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}
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public static void Ushr_S(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx);
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}
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public static void Ushr_V(AILEmitterCtx Context)
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{
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EmitShrImmOp(Context, ShrImmFlags.VectorZx);
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}
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public static void Usra_S(AILEmitterCtx Context)
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{
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EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate);
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}
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public static void Usra_V(AILEmitterCtx Context)
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{
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EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate);
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}
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private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
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{
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//This instruction shifts the value on vector A by the number of bits
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//specified on the signed, lower 8 bits of vector B. If the shift value
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//is greater or equal to the data size of each lane, then the result is zero.
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//Additionally, negative shifts produces right shifts by the negated shift value.
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int MaxShift = 8 << Op.Size;
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Action Emit = () =>
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{
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AILLabel LblShl = new AILLabel();
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AILLabel LblZero = new AILLabel();
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AILLabel LblEnd = new AILLabel();
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void EmitShift(OpCode ILOp)
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{
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(MaxShift);
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Context.Emit(OpCodes.Bge_S, LblZero);
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Context.Emit(ILOp);
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Context.Emit(OpCodes.Br_S, LblEnd);
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}
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Context.Emit(OpCodes.Conv_I1);
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Context.Emit(OpCodes.Dup);
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Context.EmitLdc_I4(0);
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Context.Emit(OpCodes.Bge_S, LblShl);
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Context.Emit(OpCodes.Neg);
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EmitShift(Signed
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? OpCodes.Shr
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: OpCodes.Shr_Un);
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Context.MarkLabel(LblShl);
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EmitShift(OpCodes.Shl);
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Context.MarkLabel(LblZero);
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Context.Emit(OpCodes.Pop);
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Context.Emit(OpCodes.Pop);
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Context.EmitLdc_I8(0);
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Context.MarkLabel(LblEnd);
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};
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if (Signed)
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{
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EmitVectorBinaryOpSx(Context, Emit);
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}
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else
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{
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EmitVectorBinaryOpZx(Context, Emit);
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}
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}
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[Flags]
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private enum ShrImmFlags
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{
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Scalar = 1 << 0,
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Signed = 1 << 1,
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Round = 1 << 2,
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Accumulate = 1 << 3,
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ScalarSx = Scalar | Signed,
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ScalarZx = Scalar,
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VectorSx = Signed,
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VectorZx = 0
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}
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private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags);
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}
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private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags);
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}
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private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags);
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}
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private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags);
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}
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private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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bool Scalar = (Flags & ShrImmFlags.Scalar) != 0;
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bool Signed = (Flags & ShrImmFlags.Signed) != 0;
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bool Round = (Flags & ShrImmFlags.Round) != 0;
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bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Bytes = Op.GetBitsCount() >> 3;
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int Elems = !Scalar ? Bytes >> Op.Size : 1;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
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if (Op.Size <= 2)
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{
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un);
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}
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else /* if (Op.Size == 3) */
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{
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EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift);
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}
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if (Accumulate)
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{
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EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
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Context.Emit(OpCodes.Add);
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}
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EmitVectorInsertTmp(Context, Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitVectorShrImmNarrowOpZx(AILEmitterCtx Context, bool Round)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Elems = 8 >> Op.Size;
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int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size + 1);
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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Context.Emit(OpCodes.Shr_Un);
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EmitVectorInsertTmp(Context, Part + Index, Op.Size);
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}
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Context.EmitLdvectmp();
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Context.EmitStvec(Op.Rd);
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if (Part == 0)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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[Flags]
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private enum ShrImmSaturatingNarrowFlags
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{
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Scalar = 1 << 0,
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SignedSrc = 1 << 1,
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SignedDst = 1 << 2,
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Round = 1 << 3,
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ScalarSxSx = Scalar | SignedSrc | SignedDst,
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ScalarSxZx = Scalar | SignedSrc,
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ScalarZxZx = Scalar,
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VectorSxSx = SignedSrc | SignedDst,
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VectorSxZx = SignedSrc,
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VectorZxZx = 0
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}
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private static void EmitRoundShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
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{
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EmitShrImmSaturatingNarrowOp(Context, ShrImmSaturatingNarrowFlags.Round | Flags);
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}
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private static void EmitShrImmSaturatingNarrowOp(AILEmitterCtx Context, ShrImmSaturatingNarrowFlags Flags)
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{
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AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
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bool Scalar = (Flags & ShrImmSaturatingNarrowFlags.Scalar) != 0;
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bool SignedSrc = (Flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0;
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bool SignedDst = (Flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0;
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bool Round = (Flags & ShrImmSaturatingNarrowFlags.Round) != 0;
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int Shift = GetImmShr(Op);
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long RoundConst = 1L << (Shift - 1);
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int Elems = !Scalar ? 8 >> Op.Size : 1;
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int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
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if (Scalar)
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{
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EmitVectorZeroLowerTmp(Context);
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}
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if (Part != 0)
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{
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Context.EmitLdvec(Op.Rd);
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Context.EmitStvectmp();
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}
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
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if (Op.Size <= 1 || !Round)
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{
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if (Round)
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{
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Context.EmitLdc_I8(RoundConst);
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Context.Emit(OpCodes.Add);
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}
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Context.EmitLdc_I4(Shift);
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|
|
|
Context.Emit(SignedSrc ? OpCodes.Shr : OpCodes.Shr_Un);
|
|
}
|
|
else /* if (Op.Size == 2 && Round) */
|
|
{
|
|
EmitShrImm_64(Context, SignedSrc, RoundConst, Shift); // Shift <= 32
|
|
}
|
|
|
|
EmitSatQ(Context, Op.Size, SignedSrc, SignedDst);
|
|
|
|
EmitVectorInsertTmp(Context, Part + Index, Op.Size);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
|
|
if (Part == 0)
|
|
{
|
|
EmitVectorZeroUpper(Context, Op.Rd);
|
|
}
|
|
}
|
|
|
|
// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
|
|
private static void EmitShrImm_64(
|
|
AILEmitterCtx Context,
|
|
bool Signed,
|
|
long RoundConst,
|
|
int Shift)
|
|
{
|
|
Context.EmitLdc_I8(RoundConst);
|
|
Context.EmitLdc_I4(Shift);
|
|
|
|
ASoftFallback.EmitCall(Context, Signed
|
|
? nameof(ASoftFallback.SignedShrImm_64)
|
|
: nameof(ASoftFallback.UnsignedShrImm_64));
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, true);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
|
|
{
|
|
EmitVectorShImmWidenBinaryOp(Context, Emit, Imm, false);
|
|
}
|
|
|
|
private static void EmitVectorShImmWidenBinaryOp(AILEmitterCtx Context, Action Emit, int Imm, bool Signed)
|
|
{
|
|
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
|
|
|
|
int Elems = 8 >> Op.Size;
|
|
|
|
int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0;
|
|
|
|
for (int Index = 0; Index < Elems; Index++)
|
|
{
|
|
EmitVectorExtract(Context, Op.Rn, Part + Index, Op.Size, Signed);
|
|
|
|
Context.EmitLdc_I4(Imm);
|
|
|
|
Emit();
|
|
|
|
EmitVectorInsertTmp(Context, Index, Op.Size + 1);
|
|
}
|
|
|
|
Context.EmitLdvectmp();
|
|
Context.EmitStvec(Op.Rd);
|
|
}
|
|
}
|
|
}
|