mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-25 06:26:01 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
24 lines
363 B
C#
24 lines
363 B
C#
using System;
|
|
|
|
namespace ChocolArm64.State
|
|
{
|
|
[Flags]
|
|
enum PState
|
|
{
|
|
TBit = 5,
|
|
EBit = 9,
|
|
|
|
VBit = 28,
|
|
CBit = 29,
|
|
ZBit = 30,
|
|
NBit = 31,
|
|
|
|
TMask = 1 << TBit,
|
|
EMask = 1 << EBit,
|
|
|
|
VMask = 1 << VBit,
|
|
CMask = 1 << CBit,
|
|
ZMask = 1 << ZBit,
|
|
NMask = 1 << NBit
|
|
}
|
|
}
|