Wunk 45ce540b9b ARMeilleure: Add gfni acceleration (#3669) ... * ARMeilleure: Add `GFNI` detection This is intended for utilizing the `gf2p8affineqb` instruction * ARMeilleure: Add `gf2p8affineqb` Not using the VEX or EVEX-form of this instruction is intentional. There are `GFNI`-chips that do not support AVX(so no VEX encoding) such as Tremont(Lakefield) chips as well as Jasper Lake. 13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299) 13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254) * ARMeilleure: Add `gfni` acceleration of `Rbit_V` Passes all `Rbit_V*` unit tests on my `i9-11900k` * ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V` Also added a fast-path for when the shift amount is greater than the size of the element. * ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V` * ARMeilleure: Increment InternalVersion * ARMeilleure: Fix Intrinsic and Assembler Table alignment `gf2p8affineqb` is the longest instruction name I know of. It shouldn't get any wider than this. * ARMeilleure: Remove SSE2+SHA requirement for GFNI * ARMeilleure Add `X86GetGf2p8LogicalShiftLeft` Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction. * ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`		2022-10-02 11:17:19 +02:00
..
Linking	A few minor documentation fixes. (#3599)	2022-08-19 18:21:06 -03:00
Optimizations	Fix tail merge from block with conditional jump to multiple returns (#3267)	2022-04-09 16:56:50 +02:00
RegisterAllocators	Removed unused usings. (#3593)	2022-08-18 18:04:54 +02:00
Unwinding	PPTC Follow-up. (#1712)	2020-12-17 20:32:09 +01:00
X86	ARMeilleure: Add gfni acceleration (#3669)	2022-10-02 11:17:19 +02:00
CompiledFunction.cs	Refactor PtcInfo (#2625)	2021-09-14 01:23:37 +02:00