mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-05 04:12:03 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
218 lines
7.4 KiB
C#
218 lines
7.4 KiB
C#
using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using static ARMeilleure.IntermediateRepresentation.OperandHelper;
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namespace ARMeilleure.Instructions
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{
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static class InstEmitHelper
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{
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public static bool IsThumb(OpCode op)
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{
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return op is OpCodeT16;
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}
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public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)
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{
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Operand value = GetIntOrZR(context, rm);
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switch (type)
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{
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case IntType.UInt8: value = context.ZeroExtend8 (value.Type, value); break;
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case IntType.UInt16: value = context.ZeroExtend16(value.Type, value); break;
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case IntType.UInt32: value = context.ZeroExtend32(value.Type, value); break;
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case IntType.Int8: value = context.SignExtend8 (value.Type, value); break;
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case IntType.Int16: value = context.SignExtend16(value.Type, value); break;
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case IntType.Int32: value = context.SignExtend32(value.Type, value); break;
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}
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return value;
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}
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public static Operand GetIntA32(ArmEmitterContext context, int regIndex)
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{
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if (regIndex == RegisterAlias.Aarch32Pc)
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{
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OpCode32 op = (OpCode32)context.CurrOp;
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return Const((int)op.GetPc());
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}
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else
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{
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return GetIntOrSP(context, GetRegisterAlias(context.Mode, regIndex));
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}
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}
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public static void SetIntA32(ArmEmitterContext context, int regIndex, Operand value)
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{
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if (regIndex == RegisterAlias.Aarch32Pc)
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{
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context.StoreToContext();
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EmitBxWritePc(context, value);
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}
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else
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{
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SetIntOrSP(context, GetRegisterAlias(context.Mode, regIndex), value);
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}
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}
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public static int GetRegisterAlias(Aarch32Mode mode, int regIndex)
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{
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// Only registers >= 8 are banked,
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// with registers in the range [8, 12] being
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// banked for the FIQ mode, and registers
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// 13 and 14 being banked for all modes.
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if ((uint)regIndex < 8)
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{
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return regIndex;
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}
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return GetBankedRegisterAlias(mode, regIndex);
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}
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public static int GetBankedRegisterAlias(Aarch32Mode mode, int regIndex)
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{
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switch (regIndex)
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{
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case 8: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R8Fiq
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: RegisterAlias.R8Usr;
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case 9: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R9Fiq
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: RegisterAlias.R9Usr;
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case 10: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R10Fiq
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: RegisterAlias.R10Usr;
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case 11: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R11Fiq
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: RegisterAlias.R11Usr;
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case 12: return mode == Aarch32Mode.Fiq
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? RegisterAlias.R12Fiq
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: RegisterAlias.R12Usr;
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case 13:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.System: return RegisterAlias.SpUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.SpFiq;
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case Aarch32Mode.Irq: return RegisterAlias.SpIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc;
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case Aarch32Mode.Abort: return RegisterAlias.SpAbt;
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case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp;
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case Aarch32Mode.Undefined: return RegisterAlias.SpUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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case 14:
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switch (mode)
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{
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case Aarch32Mode.User:
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case Aarch32Mode.Hypervisor:
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case Aarch32Mode.System: return RegisterAlias.LrUsr;
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case Aarch32Mode.Fiq: return RegisterAlias.LrFiq;
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case Aarch32Mode.Irq: return RegisterAlias.LrIrq;
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case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc;
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case Aarch32Mode.Abort: return RegisterAlias.LrAbt;
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case Aarch32Mode.Undefined: return RegisterAlias.LrUnd;
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default: throw new ArgumentException(nameof(mode));
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}
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default: throw new ArgumentOutOfRangeException(nameof(regIndex));
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}
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}
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public static void EmitBxWritePc(ArmEmitterContext context, Operand pc)
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{
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Operand mode = context.BitwiseAnd(pc, Const(1));
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SetFlag(context, PState.TFlag, mode);
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Operand lblArmMode = Label();
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context.BranchIfTrue(lblArmMode, mode);
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context.Return(context.ZeroExtend32(OperandType.I64, context.BitwiseAnd(pc, Const(~1))));
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context.MarkLabel(lblArmMode);
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context.Return(context.ZeroExtend32(OperandType.I64, context.BitwiseAnd(pc, Const(~3))));
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}
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public static Operand GetIntOrZR(ArmEmitterContext context, int regIndex)
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{
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if (regIndex == RegisterConsts.ZeroIndex)
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{
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OperandType type = context.CurrOp.GetOperandType();
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return type == OperandType.I32 ? Const(0) : Const(0L);
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}
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else
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{
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return GetIntOrSP(context, regIndex);
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}
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}
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public static void SetIntOrZR(ArmEmitterContext context, int regIndex, Operand value)
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{
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if (regIndex == RegisterConsts.ZeroIndex)
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{
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return;
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}
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SetIntOrSP(context, regIndex, value);
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}
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public static Operand GetIntOrSP(ArmEmitterContext context, int regIndex)
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{
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Operand value = Register(regIndex, RegisterType.Integer, OperandType.I64);
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if (context.CurrOp.RegisterSize == RegisterSize.Int32)
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{
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value = context.ConvertI64ToI32(value);
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}
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return value;
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}
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public static void SetIntOrSP(ArmEmitterContext context, int regIndex, Operand value)
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{
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Operand reg = Register(regIndex, RegisterType.Integer, OperandType.I64);
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if (value.Type == OperandType.I32)
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{
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value = context.ZeroExtend32(OperandType.I64, value);
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}
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context.Copy(reg, value);
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}
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public static Operand GetVec(int regIndex)
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{
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return Register(regIndex, RegisterType.Vector, OperandType.V128);
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}
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public static Operand GetFlag(PState stateFlag)
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{
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return Register((int)stateFlag, RegisterType.Flag, OperandType.I32);
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}
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public static void SetFlag(ArmEmitterContext context, PState stateFlag, Operand value)
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{
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context.Copy(GetFlag(stateFlag), value);
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context.MarkFlagSet(stateFlag);
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}
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}
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}
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