mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-05 04:02:00 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
367 lines
No EOL
9.7 KiB
C#
367 lines
No EOL
9.7 KiB
C#
using ARMeilleure.Memory;
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using ARMeilleure.State;
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using System;
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namespace ARMeilleure.Instructions
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{
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static class NativeInterface
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{
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private const int ErgSizeLog2 = 4;
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private class ThreadContext
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{
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public ExecutionContext Context { get; }
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public MemoryManager Memory { get; }
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public ulong ExclusiveAddress { get; set; }
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public ulong ExclusiveValueLow { get; set; }
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public ulong ExclusiveValueHigh { get; set; }
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public ThreadContext(ExecutionContext context, MemoryManager memory)
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{
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Context = context;
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Memory = memory;
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ExclusiveAddress = ulong.MaxValue;
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}
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}
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[ThreadStatic]
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private static ThreadContext _context;
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public static void RegisterThread(ExecutionContext context, MemoryManager memory)
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{
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_context = new ThreadContext(context, memory);
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}
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public static void UnregisterThread()
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{
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_context = null;
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}
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public static void Break(ulong address, int imm)
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{
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Statistics.PauseTimer();
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GetContext().OnBreak(address, imm);
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Statistics.ResumeTimer();
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}
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public static void SupervisorCall(ulong address, int imm)
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{
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Statistics.PauseTimer();
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GetContext().OnSupervisorCall(address, imm);
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Statistics.ResumeTimer();
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}
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public static void Undefined(ulong address, int opCode)
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{
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Statistics.PauseTimer();
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GetContext().OnUndefined(address, opCode);
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Statistics.ResumeTimer();
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}
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#region "System registers"
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public static ulong GetCtrEl0()
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{
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return (ulong)GetContext().CtrEl0;
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}
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public static ulong GetDczidEl0()
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{
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return (ulong)GetContext().DczidEl0;
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}
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public static ulong GetFpcr()
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{
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return (ulong)GetContext().Fpcr;
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}
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public static ulong GetFpsr()
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{
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return (ulong)GetContext().Fpsr;
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}
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public static ulong GetTpidrEl0()
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{
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return (ulong)GetContext().TpidrEl0;
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}
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public static ulong GetTpidr()
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{
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return (ulong)GetContext().Tpidr;
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}
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public static ulong GetCntfrqEl0()
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{
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return GetContext().CntfrqEl0;
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}
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public static ulong GetCntpctEl0()
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{
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return GetContext().CntpctEl0;
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}
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public static void SetFpcr(ulong value)
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{
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GetContext().Fpcr = (FPCR)value;
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}
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public static void SetFpsr(ulong value)
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{
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GetContext().Fpsr = (FPSR)value;
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}
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public static void SetTpidrEl0(ulong value)
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{
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GetContext().TpidrEl0 = (long)value;
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}
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#endregion
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#region "Read"
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public static byte ReadByte(ulong address)
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{
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return GetMemoryManager().ReadByte((long)address);
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}
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public static ushort ReadUInt16(ulong address)
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{
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return GetMemoryManager().ReadUInt16((long)address);
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}
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public static uint ReadUInt32(ulong address)
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{
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return GetMemoryManager().ReadUInt32((long)address);
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}
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public static ulong ReadUInt64(ulong address)
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{
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return GetMemoryManager().ReadUInt64((long)address);
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}
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public static V128 ReadVector128(ulong address)
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{
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return GetMemoryManager().ReadVector128((long)address);
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}
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#endregion
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#region "Read exclusive"
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public static byte ReadByteExclusive(ulong address)
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{
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byte value = _context.Memory.ReadByte((long)address);
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_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
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_context.ExclusiveValueLow = value;
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_context.ExclusiveValueHigh = 0;
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return value;
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}
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public static ushort ReadUInt16Exclusive(ulong address)
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{
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ushort value = _context.Memory.ReadUInt16((long)address);
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_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
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_context.ExclusiveValueLow = value;
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_context.ExclusiveValueHigh = 0;
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return value;
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}
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public static uint ReadUInt32Exclusive(ulong address)
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{
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uint value = _context.Memory.ReadUInt32((long)address);
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_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
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_context.ExclusiveValueLow = value;
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_context.ExclusiveValueHigh = 0;
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return value;
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}
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public static ulong ReadUInt64Exclusive(ulong address)
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{
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ulong value = _context.Memory.ReadUInt64((long)address);
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_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
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_context.ExclusiveValueLow = value;
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_context.ExclusiveValueHigh = 0;
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return value;
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}
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public static V128 ReadVector128Exclusive(ulong address)
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{
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V128 value = _context.Memory.AtomicLoadInt128((long)address);
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_context.ExclusiveAddress = GetMaskedExclusiveAddress(address);
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_context.ExclusiveValueLow = value.GetUInt64(0);
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_context.ExclusiveValueHigh = value.GetUInt64(1);
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return value;
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}
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#endregion
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#region "Write"
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public static void WriteByte(ulong address, byte value)
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{
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GetMemoryManager().WriteByte((long)address, value);
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}
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public static void WriteUInt16(ulong address, ushort value)
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{
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GetMemoryManager().WriteUInt16((long)address, value);
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}
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public static void WriteUInt32(ulong address, uint value)
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{
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GetMemoryManager().WriteUInt32((long)address, value);
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}
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public static void WriteUInt64(ulong address, ulong value)
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{
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GetMemoryManager().WriteUInt64((long)address, value);
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}
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public static void WriteVector128(ulong address, V128 value)
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{
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GetMemoryManager().WriteVector128((long)address, value);
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}
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#endregion
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#region "Write exclusive"
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public static int WriteByteExclusive(ulong address, byte value)
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{
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bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
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if (success)
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{
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success = _context.Memory.AtomicCompareExchangeByte(
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(long)address,
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(byte)_context.ExclusiveValueLow,
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(byte)value);
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if (success)
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{
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ClearExclusive();
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}
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}
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return success ? 0 : 1;
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}
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public static int WriteUInt16Exclusive(ulong address, ushort value)
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{
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bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
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if (success)
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{
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success = _context.Memory.AtomicCompareExchangeInt16(
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(long)address,
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(short)_context.ExclusiveValueLow,
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(short)value);
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if (success)
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{
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ClearExclusive();
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}
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}
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return success ? 0 : 1;
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}
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public static int WriteUInt32Exclusive(ulong address, uint value)
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{
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bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
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if (success)
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{
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success = _context.Memory.AtomicCompareExchangeInt32(
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(long)address,
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(int)_context.ExclusiveValueLow,
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(int)value);
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if (success)
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{
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ClearExclusive();
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}
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}
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return success ? 0 : 1;
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}
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public static int WriteUInt64Exclusive(ulong address, ulong value)
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{
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bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
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if (success)
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{
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success = _context.Memory.AtomicCompareExchangeInt64(
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(long)address,
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(long)_context.ExclusiveValueLow,
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(long)value);
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if (success)
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{
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ClearExclusive();
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}
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}
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return success ? 0 : 1;
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}
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public static int WriteVector128Exclusive(ulong address, V128 value)
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{
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bool success = _context.ExclusiveAddress == GetMaskedExclusiveAddress(address);
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if (success)
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{
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V128 expected = new V128(_context.ExclusiveValueLow, _context.ExclusiveValueHigh);
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success = _context.Memory.AtomicCompareExchangeInt128((long)address, expected, value);
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if (success)
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{
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ClearExclusive();
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}
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}
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return success ? 0 : 1;
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}
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#endregion
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private static ulong GetMaskedExclusiveAddress(ulong address)
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{
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return address & ~((4UL << ErgSizeLog2) - 1);
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}
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public static void ClearExclusive()
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{
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_context.ExclusiveAddress = ulong.MaxValue;
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}
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public static void CheckSynchronization()
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{
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Statistics.PauseTimer();
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GetContext().CheckInterrupt();
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Statistics.ResumeTimer();
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}
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public static ExecutionContext GetContext()
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{
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return _context.Context;
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}
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public static MemoryManager GetMemoryManager()
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{
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return _context.Memory;
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}
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}
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} |