mirror of
https://github.com/Ryujinx/Ryujinx.git
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a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
157 lines
No EOL
4.6 KiB
C#
157 lines
No EOL
4.6 KiB
C#
using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.Memory;
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using System;
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using System.Runtime.InteropServices;
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namespace ARMeilleure.State
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{
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class NativeContext : IDisposable
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{
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private const int IntSize = 8;
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private const int VecSize = 16;
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private const int FlagSize = 4;
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private const int ExtraSize = 4;
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private const int TotalSize = RegisterConsts.IntRegsCount * IntSize +
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RegisterConsts.VecRegsCount * VecSize +
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RegisterConsts.FlagsCount * FlagSize + ExtraSize;
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public IntPtr BasePtr { get; }
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public NativeContext()
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{
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BasePtr = MemoryManagement.Allocate(TotalSize);
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}
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public ulong GetX(int index)
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{
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if ((uint)index >= RegisterConsts.IntRegsCount)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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return (ulong)Marshal.ReadInt64(BasePtr, index * IntSize);
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}
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public void SetX(int index, ulong value)
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{
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if ((uint)index >= RegisterConsts.IntRegsCount)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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Marshal.WriteInt64(BasePtr, index * IntSize, (long)value);
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}
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public V128 GetV(int index)
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{
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if ((uint)index >= RegisterConsts.IntRegsCount)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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int offset = RegisterConsts.IntRegsCount * IntSize + index * VecSize;
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return new V128(
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Marshal.ReadInt64(BasePtr, offset + 0),
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Marshal.ReadInt64(BasePtr, offset + 8));
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}
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public void SetV(int index, V128 value)
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{
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if ((uint)index >= RegisterConsts.IntRegsCount)
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{
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throw new ArgumentOutOfRangeException(nameof(index));
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}
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int offset = RegisterConsts.IntRegsCount * IntSize + index * VecSize;
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Marshal.WriteInt64(BasePtr, offset + 0, value.GetInt64(0));
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Marshal.WriteInt64(BasePtr, offset + 8, value.GetInt64(1));
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}
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public bool GetPstateFlag(PState flag)
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{
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if ((uint)flag >= RegisterConsts.FlagsCount)
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{
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throw new ArgumentException($"Invalid flag \"{flag}\" specified.");
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}
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int offset =
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RegisterConsts.IntRegsCount * IntSize +
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RegisterConsts.VecRegsCount * VecSize + (int)flag * FlagSize;
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int value = Marshal.ReadInt32(BasePtr, offset);
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return value != 0;
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}
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public void SetPstateFlag(PState flag, bool value)
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{
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if ((uint)flag >= RegisterConsts.FlagsCount)
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{
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throw new ArgumentException($"Invalid flag \"{flag}\" specified.");
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}
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int offset =
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RegisterConsts.IntRegsCount * IntSize +
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RegisterConsts.VecRegsCount * VecSize + (int)flag * FlagSize;
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Marshal.WriteInt32(BasePtr, offset, value ? 1 : 0);
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}
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public int GetCounter()
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{
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return Marshal.ReadInt32(BasePtr, GetCounterOffset());
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}
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public void SetCounter(int value)
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{
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Marshal.WriteInt32(BasePtr, GetCounterOffset(), value);
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}
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public static int GetRegisterOffset(Register reg)
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{
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int offset, size;
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if (reg.Type == RegisterType.Integer)
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{
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offset = reg.Index * IntSize;
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size = IntSize;
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}
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else if (reg.Type == RegisterType.Vector)
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{
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offset = RegisterConsts.IntRegsCount * IntSize + reg.Index * VecSize;
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size = VecSize;
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}
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else /* if (reg.Type == RegisterType.Flag) */
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{
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offset = RegisterConsts.IntRegsCount * IntSize +
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RegisterConsts.VecRegsCount * VecSize + reg.Index * FlagSize;
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size = FlagSize;
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}
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if ((uint)(offset + size) > (uint)TotalSize)
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{
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throw new ArgumentException("Invalid register.");
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}
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return offset;
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}
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public static int GetCounterOffset()
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{
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return RegisterConsts.IntRegsCount * IntSize +
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RegisterConsts.VecRegsCount * VecSize +
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RegisterConsts.FlagsCount * FlagSize;
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}
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public void Dispose()
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{
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MemoryManagement.Free(BasePtr);
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}
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}
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} |