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Ryujinx/ARMeilleure/Instructions
LDj3SNuD e36e97c64d
CPU: This PR fixes Fpscr, among other things. ()
* CPU: This PR fixes Fpscr, among other things.

* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

* Fix Vcmp & Vcmpe opcode table.

* Revert "Fix Vcmp & Vcmpe opcode table."

This reverts commit c117d9410d.

* Address PR feedbacks.
2020-08-08 17:18:51 +02:00
..
CryptoHelper.cs
InstEmitAlu.cs
InstEmitAlu32.cs
InstEmitAluHelper.cs
InstEmitBfm.cs
InstEmitCcmp.cs
InstEmitCsel.cs
InstEmitDiv.cs
InstEmitException.cs
InstEmitException32.cs
InstEmitFlow.cs Generalize tail continues () 2020-06-18 13:37:21 +10:00
InstEmitFlow32.cs
InstEmitFlowHelper.cs
InstEmitHash.cs Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. () 2020-07-13 20:48:14 +10:00
InstEmitHash32.cs
InstEmitHashHelper.cs
InstEmitHelper.cs
InstEmitMemory.cs Add a new JIT compiler for CPU code () 2019-08-08 21:56:22 +03:00
InstEmitMemory32.cs
InstEmitMemoryEx.cs
InstEmitMemoryEx32.cs Implement inline memory load/store exclusive and ordered () 2020-07-30 11:29:28 -03:00
InstEmitMemoryExHelper.cs
InstEmitMemoryHelper.cs
InstEmitMove.cs
InstEmitMul.cs
InstEmitMul32.cs Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions () 2020-03-01 07:51:55 +11:00
InstEmitSimdArithmetic.cs
InstEmitSimdArithmetic32.cs CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. () 2020-07-17 10:57:49 -03:00
InstEmitSimdCmp.cs
InstEmitSimdCmp32.cs CPU: This PR fixes Fpscr, among other things. () 2020-08-08 17:18:51 +02:00
InstEmitSimdCrypto.cs
InstEmitSimdCrypto32.cs
InstEmitSimdCvt.cs
InstEmitSimdCvt32.cs
InstEmitSimdHash.cs
InstEmitSimdHelper.cs
InstEmitSimdHelper32.cs
InstEmitSimdLogical.cs
InstEmitSimdLogical32.cs
InstEmitSimdMemory.cs
InstEmitSimdMemory32.cs
InstEmitSimdMove.cs
InstEmitSimdMove32.cs
InstEmitSimdShift.cs
InstEmitSimdShift32.cs
InstEmitSystem.cs
InstEmitSystem32.cs CPU: This PR fixes Fpscr, among other things. () 2020-08-08 17:18:51 +02:00
InstName.cs
NativeInterface.cs
SoftFallback.cs
SoftFloat.cs