mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-24 01:32:02 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
462 lines
12 KiB
C#
462 lines
12 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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namespace ChocolArm64.Instructions
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{
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static class InstEmitAluHelper
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{
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public static void EmitAdcsCCheck(ILEmitterCtx context)
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{
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//C = (Rd == Rn && CIn) || Rd < Rn
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context.EmitSttmp();
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context.EmitLdtmp();
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context.EmitLdtmp();
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EmitAluLoadRn(context);
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context.Emit(OpCodes.Ceq);
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context.EmitLdflg((int)PState.CBit);
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context.Emit(OpCodes.And);
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context.EmitLdtmp();
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EmitAluLoadRn(context);
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context.Emit(OpCodes.Clt_Un);
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context.Emit(OpCodes.Or);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitAddsCCheck(ILEmitterCtx context)
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{
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//C = Rd < Rn
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context.Emit(OpCodes.Dup);
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EmitAluLoadRn(context);
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context.Emit(OpCodes.Clt_Un);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitAddsVCheck(ILEmitterCtx context)
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{
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//V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0
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context.Emit(OpCodes.Dup);
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EmitAluLoadRn(context);
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context.Emit(OpCodes.Xor);
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EmitAluLoadOpers(context);
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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context.EmitLdc_I(0);
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context.Emit(OpCodes.Clt);
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context.EmitStflg((int)PState.VBit);
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}
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public static void EmitSbcsCCheck(ILEmitterCtx context)
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{
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//C = (Rn == Rm && CIn) || Rn > Rm
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EmitAluLoadOpers(context);
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context.Emit(OpCodes.Ceq);
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context.EmitLdflg((int)PState.CBit);
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context.Emit(OpCodes.And);
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EmitAluLoadOpers(context);
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context.Emit(OpCodes.Cgt_Un);
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context.Emit(OpCodes.Or);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitSubsCCheck(ILEmitterCtx context)
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{
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//C = Rn == Rm || Rn > Rm = !(Rn < Rm)
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EmitAluLoadOpers(context);
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context.Emit(OpCodes.Clt_Un);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.Xor);
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context.EmitStflg((int)PState.CBit);
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}
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public static void EmitSubsVCheck(ILEmitterCtx context)
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{
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//V = (Rd ^ Rn) & (Rn ^ Rm) < 0
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context.Emit(OpCodes.Dup);
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EmitAluLoadRn(context);
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context.Emit(OpCodes.Xor);
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EmitAluLoadOpers(context);
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.And);
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context.EmitLdc_I(0);
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context.Emit(OpCodes.Clt);
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context.EmitStflg((int)PState.VBit);
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}
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public static void EmitAluLoadRm(ILEmitterCtx context)
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{
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if (context.CurrOp is IOpCodeAluRs64 op)
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{
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context.EmitLdintzr(op.Rm);
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}
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else if (context.CurrOp is OpCode32AluRsImm op32)
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{
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InstEmit32Helper.EmitLoadFromRegister(context, op32.Rm);
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}
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else
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{
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throw new InvalidOperationException();
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}
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}
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public static void EmitAluLoadOpers(ILEmitterCtx context, bool setCarry = true)
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{
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EmitAluLoadRn(context);
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EmitAluLoadOper2(context, setCarry);
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}
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public static void EmitAluLoadRn(ILEmitterCtx context)
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{
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if (context.CurrOp is IOpCodeAlu64 op)
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{
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if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs64)
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{
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context.EmitLdintzr(op.Rn);
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}
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else
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{
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context.EmitLdint(op.Rn);
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}
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}
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else if (context.CurrOp is IOpCode32Alu op32)
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{
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InstEmit32Helper.EmitLoadFromRegister(context, op32.Rn);
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}
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else
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{
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throw new InvalidOperationException();
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}
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}
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public static void EmitAluLoadOper2(ILEmitterCtx context, bool setCarry = true)
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{
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switch (context.CurrOp)
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{
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//ARM32.
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case OpCode32AluImm op:
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context.EmitLdc_I4(op.Imm);
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if (op.SetFlags && op.IsRotated)
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{
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context.EmitLdc_I4((int)((uint)op.Imm >> 31));
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context.EmitStflg((int)PState.CBit);
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}
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break;
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case OpCode32AluRsImm op:
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EmitLoadRmShiftedByImmediate(context, op, setCarry);
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break;
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case OpCodeT16AluImm8 op:
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context.EmitLdc_I4(op.Imm);
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break;
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//ARM64.
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case IOpCodeAluImm64 op:
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context.EmitLdc_I(op.Imm);
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break;
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case IOpCodeAluRs64 op:
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context.EmitLdintzr(op.Rm);
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: context.EmitLsl(op.Shift); break;
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case ShiftType.Lsr: context.EmitLsr(op.Shift); break;
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case ShiftType.Asr: context.EmitAsr(op.Shift); break;
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case ShiftType.Ror: context.EmitRor(op.Shift); break;
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}
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break;
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case IOpCodeAluRx64 op:
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context.EmitLdintzr(op.Rm);
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context.EmitCast(op.IntType);
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context.EmitLsl(op.Shift);
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break;
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default: throw new InvalidOperationException();
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}
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}
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public static void EmitSetNzcv(ILEmitterCtx context)
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{
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.VBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Dup);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.ZBit);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.Shr);
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context.Emit(OpCodes.Ldc_I4_1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.NBit);
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}
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//ARM32 helpers.
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private static void EmitLoadRmShiftedByImmediate(ILEmitterCtx context, OpCode32AluRsImm op, bool setCarry)
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{
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int shift = op.Imm;
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if (shift == 0)
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{
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switch (op.ShiftType)
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{
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case ShiftType.Lsr: shift = 32; break;
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case ShiftType.Asr: shift = 32; break;
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case ShiftType.Ror: shift = 1; break;
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}
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}
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context.EmitLdint(op.Rm);
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if (shift != 0)
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{
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setCarry &= op.SetFlags;
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switch (op.ShiftType)
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{
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case ShiftType.Lsl: EmitLslC(context, setCarry, shift); break;
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case ShiftType.Lsr: EmitLsrC(context, setCarry, shift); break;
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case ShiftType.Asr: EmitAsrC(context, setCarry, shift); break;
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case ShiftType.Ror:
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if (op.Imm != 0)
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{
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EmitRorC(context, setCarry, shift);
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}
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else
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{
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EmitRrxC(context, setCarry);
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}
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break;
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}
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}
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}
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private static void EmitLslC(ILEmitterCtx context, bool setCarry, int shift)
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{
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if ((uint)shift > 32)
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{
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EmitShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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}
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else
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{
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context.Emit(OpCodes.Pop);
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}
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context.EmitLdc_I4(0);
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}
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else
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{
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLsr(32 - shift);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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}
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context.EmitLsl(shift);
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}
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}
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private static void EmitLsrC(ILEmitterCtx context, bool setCarry, int shift)
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{
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if ((uint)shift > 32)
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{
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EmitShiftByMoreThan32(context, setCarry);
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}
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else if (shift == 32)
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{
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if (setCarry)
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{
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context.EmitLsr(31);
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context.EmitStflg((int)PState.CBit);
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}
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else
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{
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context.Emit(OpCodes.Pop);
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}
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context.EmitLdc_I4(0);
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}
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else
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{
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context.Emit(OpCodes.Dup);
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context.EmitLsr(shift - 1);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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context.EmitLsr(shift);
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}
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}
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private static void EmitShiftByMoreThan32(ILEmitterCtx context, bool setCarry)
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{
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context.Emit(OpCodes.Pop);
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context.EmitLdc_I4(0);
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitStflg((int)PState.CBit);
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}
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}
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private static void EmitAsrC(ILEmitterCtx context, bool setCarry, int shift)
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{
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if ((uint)shift >= 32)
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{
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context.EmitAsr(31);
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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}
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}
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else
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{
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLsr(shift - 1);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitStflg((int)PState.CBit);
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}
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context.EmitAsr(shift);
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}
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}
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private static void EmitRorC(ILEmitterCtx context, bool setCarry, int shift)
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{
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shift &= 0x1f;
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context.EmitRor(shift);
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLsr(31);
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context.EmitStflg((int)PState.CBit);
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}
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}
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private static void EmitRrxC(ILEmitterCtx context, bool setCarry)
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{
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//Rotate right by 1 with carry.
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if (setCarry)
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{
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context.Emit(OpCodes.Dup);
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context.EmitLdc_I4(1);
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context.Emit(OpCodes.And);
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context.EmitSttmp();
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}
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context.EmitLsr(1);
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context.EmitLdflg((int)PState.CBit);
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context.EmitLsl(31);
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context.Emit(OpCodes.Or);
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if (setCarry)
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{
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context.EmitLdtmp();
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context.EmitStflg((int)PState.CBit);
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}
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}
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}
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}
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