mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-24 02:46:03 +00:00
a731ab3a2a
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
351 lines
No EOL
11 KiB
C#
351 lines
No EOL
11 KiB
C#
using ARMeilleure.Instructions;
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using ARMeilleure.Memory;
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using ARMeilleure.State;
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using System;
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using System.Collections.Concurrent;
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using System.Collections.Generic;
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using System.Reflection.Emit;
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namespace ARMeilleure.Decoders
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{
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static class Decoder
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{
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private delegate object MakeOp(InstDescriptor inst, ulong address, int opCode);
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private static ConcurrentDictionary<Type, MakeOp> _opActivators;
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static Decoder()
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{
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_opActivators = new ConcurrentDictionary<Type, MakeOp>();
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}
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public static Block[] DecodeBasicBlock(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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Block block = new Block(address);
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FillBlock(memory, mode, block, ulong.MaxValue);
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return new Block[] { block };
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}
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public static Block[] DecodeFunction(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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List<Block> blocks = new List<Block>();
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Queue<Block> workQueue = new Queue<Block>();
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Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
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Block GetBlock(ulong blkAddress)
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{
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if (!visited.TryGetValue(blkAddress, out Block block))
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{
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block = new Block(blkAddress);
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workQueue.Enqueue(block);
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visited.Add(blkAddress, block);
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}
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return block;
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}
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GetBlock(address);
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while (workQueue.TryDequeue(out Block currBlock))
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{
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// Check if the current block is inside another block.
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if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
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{
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Block nBlock = blocks[nBlkIndex];
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if (nBlock.Address == currBlock.Address)
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{
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throw new InvalidOperationException("Found duplicate block address on the list.");
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}
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nBlock.Split(currBlock);
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blocks.Insert(nBlkIndex + 1, currBlock);
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continue;
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}
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// If we have a block after the current one, set the limit address.
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ulong limitAddress = ulong.MaxValue;
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if (nBlkIndex != blocks.Count)
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{
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Block nBlock = blocks[nBlkIndex];
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int nextIndex = nBlkIndex + 1;
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if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
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{
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limitAddress = blocks[nextIndex].Address;
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}
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else if (nBlock.Address > currBlock.Address)
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{
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limitAddress = blocks[nBlkIndex].Address;
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}
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}
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FillBlock(memory, mode, currBlock, limitAddress);
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if (currBlock.OpCodes.Count != 0)
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{
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// Set child blocks. "Branch" is the block the branch instruction
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// points to (when taken), "Next" is the block at the next address,
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// executed when the branch is not taken. For Unconditional Branches
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// (except BL/BLR that are sub calls) or end of executable, Next is null.
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OpCode lastOp = currBlock.GetLastOp();
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bool isCall = IsCall(lastOp);
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if (lastOp is IOpCodeBImm op && !isCall)
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{
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currBlock.Branch = GetBlock((ulong)op.Immediate);
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}
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if (!IsUnconditionalBranch(lastOp) /*|| isCall*/)
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{
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currBlock.Next = GetBlock(currBlock.EndAddress);
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}
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}
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// Insert the new block on the list (sorted by address).
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if (blocks.Count != 0)
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{
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Block nBlock = blocks[nBlkIndex];
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blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
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}
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else
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{
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blocks.Add(currBlock);
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}
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}
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return blocks.ToArray();
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}
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private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
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{
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index = 0;
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int left = 0;
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int right = blocks.Count - 1;
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while (left <= right)
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{
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int size = right - left;
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int middle = left + (size >> 1);
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Block block = blocks[middle];
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index = middle;
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if (address >= block.Address && address < block.EndAddress)
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{
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return true;
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}
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if (address < block.Address)
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{
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right = middle - 1;
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}
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else
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{
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left = middle + 1;
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}
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}
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return false;
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}
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private static void FillBlock(
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MemoryManager memory,
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ExecutionMode mode,
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Block block,
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ulong limitAddress)
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{
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ulong address = block.Address;
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OpCode opCode;
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do
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{
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if (address >= limitAddress)
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{
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break;
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}
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opCode = DecodeOpCode(memory, address, mode);
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block.OpCodes.Add(opCode);
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address += (ulong)opCode.OpCodeSizeInBytes;
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}
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while (!(IsBranch(opCode) || IsException(opCode)));
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block.EndAddress = address;
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}
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private static bool IsBranch(OpCode opCode)
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{
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return opCode is OpCodeBImm ||
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opCode is OpCodeBReg || IsAarch32Branch(opCode);
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}
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private static bool IsUnconditionalBranch(OpCode opCode)
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{
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return opCode is OpCodeBImmAl ||
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opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
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}
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private static bool IsAarch32UnconditionalBranch(OpCode opCode)
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{
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if (!(opCode is OpCode32 op))
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{
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return false;
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}
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// Note: On ARM32, most instructions have conditional execution,
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// so there's no "Always" (unconditional) branch like on ARM64.
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// We need to check if the condition is "Always" instead.
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return IsAarch32Branch(op) && op.Cond >= Condition.Al;
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}
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private static bool IsAarch32Branch(OpCode opCode)
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{
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// Note: On ARM32, most ALU operations can write to R15 (PC),
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// so we must consider such operations as a branch in potential aswell.
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if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
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{
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return true;
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}
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// Same thing for memory operations. We have the cases where PC is a target
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// register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
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// a write back to PC (wback == true && Rn == 15), however the later may
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// be "undefined" depending on the CPU, so compilers should not produce that.
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if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
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{
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int rt, rn;
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bool wBack, isLoad;
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if (opCode is IOpCode32Mem opMem)
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{
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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isLoad = opMem.IsLoad;
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// For the dual load, we also need to take into account the
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// case were Rt2 == 15 (PC).
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if (rt == 14 && opMem.Instruction.Name == InstName.Ldrd)
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{
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rt = RegisterAlias.Aarch32Pc;
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}
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}
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else if (opCode is IOpCode32MemMult opMemMult)
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{
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const int pcMask = 1 << RegisterAlias.Aarch32Pc;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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}
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else
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{
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throw new NotImplementedException($"The type \"{opCode.GetType().Name}\" is not implemented on the decoder.");
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}
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if ((rt == RegisterAlias.Aarch32Pc && isLoad) ||
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(rn == RegisterAlias.Aarch32Pc && wBack))
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{
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return true;
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}
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}
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// Explicit branch instructions.
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return opCode is IOpCode32BImm ||
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opCode is IOpCode32BReg;
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}
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private static bool IsCall(OpCode opCode)
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{
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// TODO (CQ): ARM32 support.
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return opCode.Instruction.Name == InstName.Bl ||
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opCode.Instruction.Name == InstName.Blr;
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}
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private static bool IsException(OpCode opCode)
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{
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return opCode.Instruction.Name == InstName.Brk ||
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opCode.Instruction.Name == InstName.Svc ||
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opCode.Instruction.Name == InstName.Und;
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}
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public static OpCode DecodeOpCode(MemoryManager memory, ulong address, ExecutionMode mode)
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{
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int opCode = memory.ReadInt32((long)address);
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InstDescriptor inst;
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Type type;
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if (mode == ExecutionMode.Aarch64)
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{
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(inst, type) = OpCodeTable.GetInstA64(opCode);
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}
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else
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{
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if (mode == ExecutionMode.Aarch32Arm)
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{
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(inst, type) = OpCodeTable.GetInstA32(opCode);
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}
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else /* if (mode == ExecutionMode.Aarch32Thumb) */
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{
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(inst, type) = OpCodeTable.GetInstT32(opCode);
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}
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}
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if (type != null)
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{
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return MakeOpCode(inst, type, address, opCode);
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}
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else
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{
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return new OpCode(inst, address, opCode);
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}
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}
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private static OpCode MakeOpCode(InstDescriptor inst, Type type, ulong address, int opCode)
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{
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MakeOp createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
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return (OpCode)createInstance(inst, address, opCode);
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}
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private static MakeOp CacheOpActivator(Type type)
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{
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Type[] argTypes = new Type[] { typeof(InstDescriptor), typeof(ulong), typeof(int) };
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DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
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ILGenerator generator = mthd.GetILGenerator();
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generator.Emit(OpCodes.Ldarg_0);
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generator.Emit(OpCodes.Ldarg_1);
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generator.Emit(OpCodes.Ldarg_2);
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generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
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generator.Emit(OpCodes.Ret);
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return (MakeOp)mthd.CreateDelegate(typeof(MakeOp));
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}
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}
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} |