mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-29 15:06:00 +00:00
ad00fd0244
* Update OpCodeTable.cs * Update InstEmitSimdShift.cs * Update SoftFallback.cs * Update CpuTestSimdReg.cs * Nit. * Update SoftFallback.cs * Update Optimizations.cs * Update InstEmitSimdLogical.cs * Update InstEmitSimdArithmetic.cs
440 lines
15 KiB
C#
440 lines
15 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System;
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using System.Reflection.Emit;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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using static ChocolArm64.Instructions.InstEmitSimdHelper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit
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{
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public static void And_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.And));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.And));
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}
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}
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public static void Bic_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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Type[] typesAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
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EmitLdvecWithUnsignedCast(context, op.Rm, 0);
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EmitLdvecWithUnsignedCast(context, op.Rn, 0);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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EmitStvecWithUnsignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorBinaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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});
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}
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}
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public static void Bic_Vi(ILEmitterCtx context)
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{
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EmitVectorImmBinaryOp(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.And);
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});
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}
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public static void Bif_V(ILEmitterCtx context)
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{
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EmitBifBit(context, notRm: true);
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}
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public static void Bit_V(ILEmitterCtx context)
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{
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EmitBifBit(context, notRm: false);
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}
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private static void EmitBifBit(ILEmitterCtx context, bool notRm)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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if (Optimizations.UseSse2)
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{
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Type[] typesXorAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
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string nameAndNot = notRm ? nameof(Sse2.AndNot) : nameof(Sse2.And);
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EmitLdvecWithUnsignedCast(context, op.Rd, 0);
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EmitLdvecWithUnsignedCast(context, op.Rm, 0);
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EmitLdvecWithUnsignedCast(context, op.Rn, 0);
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EmitLdvecWithUnsignedCast(context, op.Rd, 0);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameAndNot, typesXorAndNot));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAndNot));
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EmitStvecWithUnsignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 2 : 1;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rd, index, 3);
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context.Emit(OpCodes.Dup);
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EmitVectorExtractZx(context, op.Rn, index, 3);
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context.Emit(OpCodes.Xor);
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EmitVectorExtractZx(context, op.Rm, index, 3);
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if (notRm)
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{
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context.Emit(OpCodes.Not);
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}
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context.Emit(OpCodes.And);
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context.Emit(OpCodes.Xor);
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EmitVectorInsert(context, op.Rd, index, 3);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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public static void Bsl_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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Type[] typesXorAnd = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
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EmitLdvecWithUnsignedCast(context, op.Rm, 0);
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context.Emit(OpCodes.Dup);
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EmitLdvecWithUnsignedCast(context, op.Rn, 0);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAnd));
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EmitLdvecWithUnsignedCast(context, op.Rd, 0);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.And), typesXorAnd));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Xor), typesXorAnd));
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EmitStvecWithUnsignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorTernaryOpZx(context, () =>
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{
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context.EmitSttmp();
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context.EmitLdtmp();
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context.Emit(OpCodes.Xor);
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context.Emit(OpCodes.And);
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context.EmitLdtmp();
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context.Emit(OpCodes.Xor);
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});
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}
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}
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public static void Eor_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.Xor));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Xor));
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}
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}
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public static void Not_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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Type[] typesSav = new Type[] { typeof(byte) };
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Type[] typesAndNot = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
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EmitLdvecWithUnsignedCast(context, op.Rn, 0);
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context.EmitLdc_I4(byte.MaxValue);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNot));
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EmitStvecWithUnsignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorUnaryOpZx(context, () => context.Emit(OpCodes.Not));
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}
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}
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public static void Orn_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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OpCodeSimdReg64 op = (OpCodeSimdReg64)context.CurrOp;
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Type[] typesSav = new Type[] { typeof(byte) };
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Type[] typesAndNotOr = new Type[] { typeof(Vector128<byte>), typeof(Vector128<byte>) };
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EmitLdvecWithUnsignedCast(context, op.Rn, 0);
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EmitLdvecWithUnsignedCast(context, op.Rm, 0);
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context.EmitLdc_I4(byte.MaxValue);
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetAllVector128), typesSav));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.AndNot), typesAndNotOr));
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Or), typesAndNotOr));
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EmitStvecWithUnsignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitVectorBinaryOpZx(context, () =>
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{
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context.Emit(OpCodes.Not);
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context.Emit(OpCodes.Or);
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});
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}
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}
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public static void Orr_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSse2)
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{
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EmitSse2Op(context, nameof(Sse2.Or));
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}
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else
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{
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EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Or));
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}
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}
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public static void Orr_Vi(ILEmitterCtx context)
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{
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EmitVectorImmBinaryOp(context, () => context.Emit(OpCodes.Or));
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}
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public static void Rbit_V(ILEmitterCtx context)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
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for (int index = 0; index < elems; index++)
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{
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EmitVectorExtractZx(context, op.Rn, index, 0);
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context.Emit(OpCodes.Conv_U4);
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SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBits8));
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context.Emit(OpCodes.Conv_U8);
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EmitVectorInsert(context, op.Rd, index, 0);
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}
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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public static void Rev16_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSsse3)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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Type[] typesSfl = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
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EmitLdvecWithSignedCast(context, op.Rn, 0); // value
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context.EmitLdc_I8(14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0); // maskE1
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context.EmitLdc_I8(06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0); // maskE0
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesSfl));
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EmitStvecWithSignedCast(context, op.Rd, 0);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitRev_V(context, containerSize: 1);
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}
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}
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public static void Rev32_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSsse3)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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Type[] typesSfl = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
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EmitLdvecWithSignedCast(context, op.Rn, op.Size); // value
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if (op.Size == 0)
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{
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context.EmitLdc_I8(12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0); // maskE1
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context.EmitLdc_I8(04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0); // maskE0
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}
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else /* if (op.Size == 1) */
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{
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context.EmitLdc_I8(13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0); // maskE1
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context.EmitLdc_I8(05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0); // maskE0
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}
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesSfl));
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitRev_V(context, containerSize: 2);
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}
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}
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public static void Rev64_V(ILEmitterCtx context)
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{
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if (Optimizations.UseSsse3)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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Type[] typesSve = new Type[] { typeof(long), typeof(long) };
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Type[] typesSfl = new Type[] { typeof(Vector128<sbyte>), typeof(Vector128<sbyte>) };
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EmitLdvecWithSignedCast(context, op.Rn, op.Size); // value
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if (op.Size == 0)
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{
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context.EmitLdc_I8(08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0); // maskE1
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context.EmitLdc_I8(00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0); // maskE0
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}
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else if (op.Size == 1)
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{
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context.EmitLdc_I8(09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0); // maskE1
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context.EmitLdc_I8(01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0); // maskE0
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}
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else /* if (op.Size == 2) */
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{
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context.EmitLdc_I8(11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0); // maskE1
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context.EmitLdc_I8(03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0); // maskE0
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}
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context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.SetVector128), typesSve));
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context.EmitCall(typeof(Ssse3).GetMethod(nameof(Ssse3.Shuffle), typesSfl));
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EmitStvecWithSignedCast(context, op.Rd, op.Size);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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else
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{
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EmitRev_V(context, containerSize: 3);
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}
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}
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private static void EmitRev_V(ILEmitterCtx context, int containerSize)
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{
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OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp;
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int bytes = op.GetBitsCount() >> 3;
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int elems = bytes >> op.Size;
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int containerMask = (1 << (containerSize - op.Size)) - 1;
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for (int index = 0; index < elems; index++)
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{
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int revIndex = index ^ containerMask;
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EmitVectorExtractZx(context, op.Rn, revIndex, op.Size);
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EmitVectorInsertTmp(context, index, op.Size);
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}
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context.EmitLdvectmp();
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context.EmitStvec(op.Rd);
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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EmitVectorZeroUpper(context, op.Rd);
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}
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}
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}
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}
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