mirror of
https://github.com/suchmememanyskill/TegraExplorer.git
synced 2024-11-26 13:52:06 +00:00
116 lines
3.3 KiB
C
116 lines
3.3 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _UART_H_
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#define _UART_H_
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#include <utils/types.h>
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#define UART_A 0
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#define UART_B 1
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#define UART_C 2
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#define UART_D 3
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#define UART_E 4
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#define BAUD_115200 115200
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#define UART_TX_IDLE BIT(0)
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#define UART_RX_RDYR BIT(1)
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#define UART_TX_FIFO_FULL BIT(8)
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#define UART_RX_FIFO_EMPTY BIT(9)
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#define UART_INVERT_RXD BIT(0)
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#define UART_INVERT_TXD BIT(1)
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#define UART_INVERT_CTS BIT(2)
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#define UART_INVERT_RTS BIT(3)
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#define UART_IER_DLAB_IE_EORD BIT(5)
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#define UART_LCR_WORD_LENGTH_8 0x3
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#define UART_LCR_STOP BIT(2)
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#define UART_LCR_DLAB BIT(7)
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#define UART_LSR_RDR BIT(0)
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#define UART_LSR_THRE BIT(5)
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#define UART_LSR_TMTY BIT(6)
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#define UART_LSR_FIFOE BIT(7)
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#define UART_IIR_FCR_EN_FIFO BIT(0)
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#define UART_IIR_FCR_RX_CLR BIT(1)
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#define UART_IIR_FCR_TX_CLR BIT(2)
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#define UART_IIR_NO_INT BIT(0)
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#define UART_IIR_INT_MASK 0xF
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/* Custom returned interrupt results. Actual interrupts are -1 */
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#define UART_IIR_NOI 0 // No interrupt.
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#define UART_IIR_MSI 1 // Modem status interrupt.
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#define UART_IIR_THRI 2 // Transmitter holding register empty.
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#define UART_IIR_RDI 3 // Receiver data interrupt.
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#define UART_IIR_ERROR 4 // Overrun Error, Parity Error, Framing Error, Break.
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#define UART_IIR_REDI 5 // Receiver end of data interrupt.
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#define UART_IIR_RDTI 7 // Receiver data timeout interrupt.
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#define UART_MCR_DTR BIT(0)
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#define UART_MCR_RTS BIT(1)
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#define UART_MCR_CTS_EN BIT(5)
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#define UART_MCR_RTS_EN BIT(6)
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typedef struct _uart_t
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{
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/* 0x00 */ vu32 UART_THR_DLAB;
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/* 0x04 */ vu32 UART_IER_DLAB;
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/* 0x08 */ vu32 UART_IIR_FCR;
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/* 0x0C */ vu32 UART_LCR;
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/* 0x10 */ vu32 UART_MCR;
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/* 0x14 */ vu32 UART_LSR;
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/* 0x18 */ vu32 UART_MSR;
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/* 0x1C */ vu32 UART_SPR;
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/* 0x20 */ vu32 UART_IRDA_CSR;
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/* 0x24 */ vu32 UART_RX_FIFO_CFG;
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/* 0x28 */ vu32 UART_MIE;
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/* 0x2C */ vu32 UART_VENDOR_STATUS;
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/* 0x30 */ u8 _pad_30[0xC];
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/* 0x3C */ vu32 UART_ASR;
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} uart_t;
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//! TODO: Commented out modes are not supported yet.
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typedef enum _uart_mode_t
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{
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UART_AO_TX_AO_RX = 0,
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//UART_MN_TX_AO_RX = UART_MCR_RTS | UART_MCR_DTR,
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UART_AO_TX_MN_RX = UART_MCR_RTS, // Up to 36 bytes read.
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//UART_MN_TX_AO_RX = UART_MCR_DTR,
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//UART_HW_TX_HW_RX = UART_MCR_RTS_EN | UART_MCR_CTS_EN,
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UART_AO_TX_HW_RX = UART_MCR_RTS_EN,
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//UART_HW_TX_AO_RX = UART_MCR_CTS_EN,
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} uart_mode_t;
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void uart_init(u32 idx, u32 baud, u32 mode);
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void uart_wait_xfer(u32 idx, u32 which);
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void uart_send(u32 idx, const u8 *buf, u32 len);
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u32 uart_recv(u32 idx, u8 *buf, u32 len);
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void uart_invert(u32 idx, bool enable, u32 invert_mask);
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void uart_set_mode(u32 idx, u32 mode);
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u32 uart_get_IIR(u32 idx);
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void uart_set_IIR(u32 idx);
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void uart_empty_fifo(u32 idx, u32 which);
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#ifdef DEBUG_UART_PORT
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void uart_printf(const char *fmt, ...);
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#endif
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#endif
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