mirror of
https://github.com/suchmememanyskill/TegraExplorer.git
synced 2024-11-26 13:52:06 +00:00
339 lines
11 KiB
C
339 lines
11 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <power/max7762x.h>
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#include <power/max77620.h>
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#include <power/max77812.h>
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#include <soc/fuse.h>
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#include <soc/i2c.h>
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#include <soc/t210.h>
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#include <utils/util.h>
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#define REGULATOR_SD 0
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#define REGULATOR_LDO 1
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#define REGULATOR_BC0 2
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#define REGULATOR_BC1 3
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typedef struct _max77620_fps_t
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{
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u8 fps_addr;
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u8 fps_src;
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u8 pd_period;
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u8 pu_period;
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} max77620_fps_t;
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typedef struct _max77621_ctrl_t
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{
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u8 ctrl1_por;
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u8 ctrl1_hos;
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u8 ctrl2_por;
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u8 ctrl2_hos;
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} max77621_ctrl_t;
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typedef struct _max77812_ctrl_t
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{
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u8 mask;
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u8 shift;
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u8 rsvd0;
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u8 rsvd1;
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} max77812_en_t;
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typedef struct _max77620_regulator_t
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{
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const char *name;
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u32 uv_step;
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u32 uv_min;
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u32 uv_default;
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u32 uv_max;
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u8 type;
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u8 volt_addr;
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u8 cfg_addr;
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u8 volt_mask;
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union {
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max77620_fps_t fps;
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max77621_ctrl_t ctrl;
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max77812_en_t enable;
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};
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} max77620_regulator_t;
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static const max77620_regulator_t _pmic_regulators[] = {
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{ "sd0", 12500, 600000, 625000, 1400000, REGULATOR_SD, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, {{ MAX77620_REG_FPS_SD0, 1, 7, 1 }} },
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{ "sd1", 12500, 600000, 1125000, 1250000, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} },
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{ "sd2", 12500, 600000, 1325000, 1350000, REGULATOR_SD, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD2, 1, 5, 2 }} },
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{ "sd3", 12500, 600000, 1800000, 1800000, REGULATOR_SD, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD3, 0, 3, 3 }} },
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{ "ldo0", 25000, 800000, 1200000, 1200000, REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
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{ "ldo1", 25000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO1, 3, 7, 0 }} },
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{ "ldo2", 50000, 800000, 1800000, 3300000, REGULATOR_LDO, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO2, 3, 7, 0 }} },
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{ "ldo3", 50000, 800000, 3100000, 3100000, REGULATOR_LDO, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO3, 3, 7, 0 }} },
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{ "ldo4", 12500, 800000, 850000, 1000000, REGULATOR_LDO, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO4, 0, 7, 1 }} },
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{ "ldo5", 50000, 800000, 1800000, 1800000, REGULATOR_LDO, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO5, 3, 7, 0 }} },
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{ "ldo6", 50000, 800000, 2900000, 2900000, REGULATOR_LDO, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO6, 3, 7, 0 }} },
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{ "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
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{ "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
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{ "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
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//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
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//{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
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};
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static u8 _max77812_get_address()
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{
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static u8 max77812_i2c_addr = 0;
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if (max77812_i2c_addr)
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return max77812_i2c_addr;
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max77812_i2c_addr =
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!(FUSE(FUSE_RESERVED_ODM28_T210B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR;
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return max77812_i2c_addr;
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}
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static u8 _max7762x_get_i2c_address(u32 id)
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{
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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// Choose the correct i2c address.
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switch (reg->type)
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{
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case REGULATOR_SD:
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case REGULATOR_LDO:
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return MAX77620_I2C_ADDR;
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case REGULATOR_BC0:
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return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR);
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case REGULATOR_BC1:
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return _max77812_get_address();
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default:
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return 0;
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}
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}
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static void _max7762x_set_reg(u8 addr, u8 reg, u8 val)
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{
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u32 retries = 100;
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while (retries)
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{
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if (i2c_send_byte(I2C_5, addr, reg, val))
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break;
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usleep(50);
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retries--;
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}
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}
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int max77620_regulator_get_status(u32 id)
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{
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if (id > REGULATOR_LDO8)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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// SD power OK status.
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if (reg->type == REGULATOR_SD)
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{
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u8 mask = 1u << (7 - id);
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return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & mask) ? 0 : 1;
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}
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// LDO power OK status.
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return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & MAX77620_LDO_CFG2_POK_MASK) ? 1 : 0;
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}
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int max77620_regulator_config_fps(u32 id)
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{
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if (id > REGULATOR_LDO8)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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// Set FPS configuration.
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_max7762x_set_reg(MAX77620_I2C_ADDR,
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reg->fps.fps_addr,
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(reg->fps.fps_src << MAX77620_FPS_SRC_SHIFT) |
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(reg->fps.pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) |
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(reg->fps.pd_period << MAX77620_FPS_PD_PERIOD_SHIFT));
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return 1;
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}
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int max7762x_regulator_set_voltage(u32 id, u32 mv)
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{
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (mv < reg->uv_min || mv > reg->uv_max)
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return 0;
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u8 addr = _max7762x_get_i2c_address(id);
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// Calculate voltage multiplier.
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u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
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u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
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val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
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// Set voltage.
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_max7762x_set_reg(addr, reg->volt_addr, val);
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// If max77621 set DVS voltage also.
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if (reg->type == REGULATOR_BC0)
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_max7762x_set_reg(addr, reg->cfg_addr, MAX77621_VOUT_ENABLE_MASK | val);
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// Wait for ramp up/down delay.
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usleep(1000);
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return 1;
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}
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int max7762x_regulator_enable(u32 id, bool enable)
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{
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u8 reg_addr;
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u8 enable_val;
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u8 enable_mask;
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u8 enable_shift;
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if (id > REGULATOR_MAX)
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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// Choose the correct i2c and register addresses and mask/shift for each type.
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switch (reg->type)
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{
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case REGULATOR_SD:
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reg_addr = reg->cfg_addr;
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enable_val = MAX77620_POWER_MODE_NORMAL;
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enable_mask = MAX77620_SD_POWER_MODE_MASK;
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enable_shift = MAX77620_SD_POWER_MODE_SHIFT;
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break;
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case REGULATOR_LDO:
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reg_addr = reg->volt_addr;
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enable_val = MAX77620_POWER_MODE_NORMAL;
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enable_mask = MAX77620_LDO_POWER_MODE_MASK;
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enable_shift = MAX77620_LDO_POWER_MODE_SHIFT;
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break;
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case REGULATOR_BC0:
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reg_addr = reg->volt_addr;
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enable_val = MAX77621_VOUT_ENABLE;
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enable_mask = MAX77621_DVC_DVS_ENABLE_MASK;
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enable_shift = MAX77621_DVC_DVS_ENABLE_SHIFT;
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break;
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case REGULATOR_BC1:
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reg_addr = reg->cfg_addr;
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enable_val = MAX77812_EN_CTRL_ENABLE;
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enable_mask = reg->enable.mask;
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enable_shift = reg->enable.shift;
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break;
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default:
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return 0;
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}
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u8 addr = _max7762x_get_i2c_address(id);
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// Read and enable/disable.
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u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
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val &= ~enable_mask;
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if (enable)
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val |= (enable_val << enable_shift);
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// Set enable.
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_max7762x_set_reg(addr, reg_addr, val);
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// Wait for enable/disable ramp delay.
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usleep(1000);
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return 1;
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}
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void max77620_config_gpio(u32 gpio_id, bool enable)
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{
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if (gpio_id > 7)
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return;
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// Configure as standard GPIO.
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u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, val & ~BIT(gpio_id));
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// Set GPIO configuration.
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if (enable)
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val = MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DIR_OUTPUT | MAX77620_CNFG_GPIO_DRV_PUSHPULL;
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else
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val = MAX77620_CNFG_GPIO_DIR_INPUT | MAX77620_CNFG_GPIO_DRV_OPENDRAIN;
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO0 + gpio_id, val);
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}
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void max77621_config_default(u32 id, bool por)
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{
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (reg->type != REGULATOR_BC0)
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return;
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u8 addr = _max7762x_get_i2c_address(id);
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if (por)
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{
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// Set voltage and disable power before changing the inductor.
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max7762x_regulator_set_voltage(id, 1000000);
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max7762x_regulator_enable(id, false);
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// Configure to default.
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por);
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por);
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}
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else
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{
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos);
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos);
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}
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}
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void max77620_config_default()
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{
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// Check if Erista OTP.
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if (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4) != 0x35)
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return;
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// Set default voltages and enable regulators.
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for (u32 i = 1; i <= REGULATOR_LDO8; i++)
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{
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max77620_regulator_config_fps(i);
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max7762x_regulator_set_voltage(i, _pmic_regulators[i].uv_default);
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if (_pmic_regulators[i].fps.fps_src != MAX77620_FPS_SRC_NONE)
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max7762x_regulator_enable(i, true);
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}
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// Enable SD0 output voltage sense and disable for SD1. Additionally disable the reserved bit.
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_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0);
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}
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// Stock HOS: disabled.
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void max77620_low_battery_monitor_config(bool enable)
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{
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_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
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MAX77620_CNFGGLBL1_LBDAC_EN |
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(enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
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MAX77620_CNFGGLBL1_LBHYST_200 |
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MAX77620_CNFGGLBL1_LBDAC_2800);
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}
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