mirror of
https://github.com/suchmememanyskill/TegraExplorer.git
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107 lines
3 KiB
C
107 lines
3 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 shuffle2
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* Copyright (c) 2018 balika011
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* Copyright (c) 2019-2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _FUSE_H_
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#define _FUSE_H_
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#include <utils/types.h>
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/*! Fuse registers. */
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#define FUSE_CTRL 0x0
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#define FUSE_ADDR 0x4
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#define FUSE_RDATA 0x8
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#define FUSE_WDATA 0xC
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#define FUSE_TIME_RD1 0x10
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#define FUSE_TIME_RD2 0x14
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#define FUSE_TIME_PGM1 0x18
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#define FUSE_TIME_PGM2 0x1C
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#define FUSE_PRIV2INTFC 0x20
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#define FUSE_FUSEBYPASS 0x24
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#define FUSE_PRIVATEKEYDISABLE 0x28
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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#define FUSE_SKU_INFO 0x110
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#define FUSE_CPU_SPEEDO_0_CALIB 0x114
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#define FUSE_CPU_IDDQ_CALIB 0x118
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#define FUSE_OPT_FT_REV 0x128
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#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
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#define FUSE_CPU_SPEEDO_2_CALIB 0x130
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#define FUSE_SOC_SPEEDO_0_CALIB 0x134
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#define FUSE_SOC_SPEEDO_1_CALIB 0x138
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#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
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#define FUSE_SOC_IDDQ_CALIB 0x140
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#define FUSE_OPT_CP_REV 0x190
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c
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#define FUSE_PRIVATE_KEY0 0x1A4
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#define FUSE_PRIVATE_KEY1 0x1A8
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#define FUSE_PRIVATE_KEY2 0x1AC
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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#define FUSE_OPT_LOT_CODE_0 0x208
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#define FUSE_OPT_LOT_CODE_1 0x20C
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#define FUSE_OPT_WAFER_ID 0x210
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_USB_CALIB_EXT 0x350
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#define FUSE_RESERVED_ODM28_T210B01 0x240
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/*! Fuse commands. */
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#define FUSE_READ 0x1
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#define FUSE_WRITE 0x2
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#define FUSE_SENSE 0x3
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#define FUSE_CMD_MASK 0x3
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/*! Fuse cache registers. */
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#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
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enum
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{
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FUSE_NX_HW_TYPE_ICOSA,
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FUSE_NX_HW_TYPE_IOWA,
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FUSE_NX_HW_TYPE_HOAG
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};
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enum
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{
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FUSE_NX_HW_STATE_PROD,
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FUSE_NX_HW_STATE_DEV
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};
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void fuse_disable_program();
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u32 fuse_read_odm(u32 idx);
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u32 fuse_read_odm_keygen_rev();
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u32 fuse_read_dramid(bool raw_id);
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u32 fuse_read_hw_state();
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u32 fuse_read_hw_type();
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u8 fuse_count_burnt(u32 val);
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void fuse_wait_idle();
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int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
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int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
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void fuse_read_array(u32 *words);
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bool fuse_check_patched_rcm();
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#endif
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