diff --git a/src/frontend/A64/decoder/a64.inc b/src/frontend/A64/decoder/a64.inc index df3e45b1..8fa17bd8 100644 --- a/src/frontend/A64/decoder/a64.inc +++ b/src/frontend/A64/decoder/a64.inc @@ -364,7 +364,7 @@ INST(DUP_elt_1, "DUP (element)", "01011 //INST(FCVTAS_1, "FCVTAS (vector)", "0101111001111001110010nnnnnddddd") //INST(FCVTAS_2, "FCVTAS (vector)", "010111100z100001110010nnnnnddddd") //INST(SCVTF_int_1, "SCVTF (vector, integer)", "0101111001111001110110nnnnnddddd") -//INST(SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd") +INST(SCVTF_int_2, "SCVTF (vector, integer)", "010111100z100001110110nnnnnddddd") //INST(FCMGT_zero_1, "FCMGT (zero)", "0101111011111000110010nnnnnddddd") //INST(FCMGT_zero_2, "FCMGT (zero)", "010111101z100000110010nnnnnddddd") //INST(FCMEQ_zero_1, "FCMEQ (zero)", "0101111011111000110110nnnnnddddd") diff --git a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp index e4c102e5..5bb8f28b 100644 --- a/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp +++ b/src/frontend/A64/translate/impl/simd_scalar_two_register_misc.cpp @@ -33,6 +33,19 @@ bool TranslatorVisitor::NEG_1(Imm<2> size, Vec Vn, Vec Vd) { return true; } +bool TranslatorVisitor::SCVTF_int_2(bool sz, Vec Vn, Vec Vd) { + const auto esize = sz ? 64 : 32; + + IR::U32U64 element = V_scalar(esize, Vn); + if (esize == 32) { + element = ir.FPS32ToSingle(element, false, true); + } else { + return InterpretThisInstruction(); + } + V_scalar(esize, Vd, element); + return true; +} + bool TranslatorVisitor::UCVTF_int_2(bool sz, Vec Vn, Vec Vd) { const auto esize = sz ? 64 : 32;