2018-03-27 00:04:16 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-08-13 09:58:24 +01:00
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#include "../soc/uart.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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2018-03-07 01:11:46 +00:00
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/* UART A, B, C, D and E. */
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static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 };
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void uart_init(u32 idx, u32 baud)
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{
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uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
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2018-12-07 20:00:19 +00:00
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// Make sure no data is being sent.
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uart_wait_idle(idx, UART_TX_IDLE);
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// Misc settings.
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2018-03-07 01:11:46 +00:00
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u32 rate = (8 * baud + 408000000) / (16 * baud);
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2018-12-07 20:00:19 +00:00
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uart->UART_IER_DLAB = 0; // Disable interrupts.
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uart->UART_MCR = 0; // Disable hardware flow control.
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uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode.
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uart->UART_THR_DLAB = (u8)rate; // Divisor latch LSB.
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uart->UART_IER_DLAB = (u8)(rate >> 8); // Divisor latch MSB.
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uart->UART_LCR = UART_LCR_WORD_LENGTH_8; // Diable DLAB.
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2018-03-07 01:11:46 +00:00
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2018-12-07 20:00:19 +00:00
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// Setup and flush fifo.
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uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_RX_CLR | UART_IIR_FCR_TX_CLR;
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2018-07-04 16:39:26 +01:00
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usleep(3 * ((baud + 999999) / baud));
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2018-12-07 20:00:19 +00:00
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uart_wait_idle(idx, UART_TX_IDLE | UART_RX_IDLE);
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2018-03-07 01:11:46 +00:00
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}
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void uart_wait_idle(u32 idx, u32 which)
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{
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uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
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2018-12-07 20:00:19 +00:00
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if (UART_TX_IDLE & which)
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{
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while (!(uart->UART_LSR & UART_LSR_TMTY))
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;
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}
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if (UART_RX_IDLE & which)
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{
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while (uart->UART_LSR & UART_LSR_RDR)
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;
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}
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2018-03-07 01:11:46 +00:00
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}
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void uart_send(u32 idx, u8 *buf, u32 len)
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{
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uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
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for (u32 i = 0; i != len; i++)
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{
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2018-12-07 20:00:19 +00:00
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while (!(uart->UART_LSR & UART_LSR_THRE))
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2018-03-07 01:11:46 +00:00
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;
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uart->UART_THR_DLAB = buf[i];
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};
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}
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void uart_recv(u32 idx, u8 *buf, u32 len)
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{
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uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
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for (u32 i = 0; i != len; i++)
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{
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2018-12-07 20:00:19 +00:00
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while (!(uart->UART_LSR & UART_LSR_RDR))
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2018-03-07 01:11:46 +00:00
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;
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buf[i] = uart->UART_THR_DLAB;
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};
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}
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