1
0
Fork 0
mirror of https://github.com/CTCaer/hekate.git synced 2024-10-30 23:41:44 +00:00
hekate/bdk/soc/ccplex.c

108 lines
4.1 KiB
C
Raw Normal View History

2018-03-27 00:04:16 +01:00
/*
2018-08-05 12:40:32 +01:00
* Copyright (c) 2018 naehrwert
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
2018-03-27 00:04:16 +01:00
#include <soc/ccplex.h>
#include <soc/i2c.h>
#include <soc/clock.h>
#include <soc/pmc.h>
#include <soc/t210.h>
#include <power/max77620.h>
#include <power/max7762x.h>
#include <utils/util.h>
2020-06-13 23:09:17 +01:00
void _ccplex_enable_power()
{
2019-02-15 23:23:14 +00:00
u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
2020-11-25 23:41:45 +00:00
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~BIT(5)); // Disable GPIO5 pinmuxing.
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
2018-08-05 12:40:32 +01:00
// Enable cores power.
2018-11-10 12:11:42 +00:00
// 1-3.x: MAX77621_NFSR_ENABLE.
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE | MAX77621_RAMP_12mV_PER_US);
2018-11-10 12:11:42 +00:00
// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
2018-11-10 12:11:42 +00:00
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
2019-09-09 13:48:49 +01:00
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
}
2020-06-13 23:09:17 +01:00
void ccplex_boot_cpu0(u32 entry)
{
2018-08-05 12:40:32 +01:00
// Set ACTIVE_CLUSER to FAST.
FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
2020-06-13 23:09:17 +01:00
_ccplex_enable_power();
2019-12-04 19:31:39 +00:00
if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
{
2019-12-04 19:31:39 +00:00
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
usleep(2);
2018-05-01 06:15:48 +01:00
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
2018-06-08 10:42:24 +01:00
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
2018-05-01 06:15:48 +01:00
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
}
2018-05-01 06:15:48 +01:00
while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
;
2018-08-05 12:40:32 +01:00
// Configure MSELECT source and enable clock.
2018-06-08 10:42:24 +01:00
CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
2020-07-17 14:50:17 +01:00
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & ~BIT(CLK_V_MSELECT)) | BIT(CLK_V_MSELECT);
2018-05-01 06:15:48 +01:00
2018-08-05 12:40:32 +01:00
// Configure initial CPU clock frequency and enable clock.
2018-05-01 06:15:48 +01:00
CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
2020-07-17 14:50:17 +01:00
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG);
clock_enable_coresight();
2018-08-05 12:40:32 +01:00
// CAR2PMC_CPU_ACK_WIDTH should be set to 0.
2018-06-08 10:42:24 +01:00
CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
2018-08-05 12:40:32 +01:00
// Enable CPU rail.
pmc_enable_partition(0, 1);
// Enable cluster 0 non-CPU rail.
pmc_enable_partition(15, 1);
// Enable CE0 rail.
pmc_enable_partition(14, 1);
2018-08-05 12:40:32 +01:00
// Request and wait for RAM repair.
FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
;
2018-11-10 12:11:42 +00:00
EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0;
2018-08-05 12:40:32 +01:00
// Set reset vector.
2019-09-09 14:56:37 +01:00
SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN;
SB(SB_AA64_RESET_HIGH) = 0;
2018-08-05 12:40:32 +01:00
// Non-secure reset vector write disable.
2019-09-09 14:56:37 +01:00
SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
2018-05-01 06:15:48 +01:00
(void)SB(SB_CSR);
2019-12-04 19:31:39 +00:00
// Tighten up the security aperture.
// MC(MC_TZ_SECURITY_CTRL) = 1;
2018-08-05 12:40:32 +01:00
// Clear MSELECT reset.
2020-07-17 14:50:17 +01:00
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= ~BIT(CLK_V_MSELECT);
2018-08-05 12:40:32 +01:00
// Clear NONCPU reset.
2018-05-01 06:15:48 +01:00
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
// Clear CPU0 reset.
// < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.
CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001;
}