mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-23 18:22:08 +00:00
642 lines
38 KiB
Modula-2
642 lines
38 KiB
Modula-2
|
EMC_DBG 8
|
||
|
|
EMC_CFG C
|
||
|
|
EMC_CONFIG_SAMPLE_DELAY 5f0
|
||
|
|
EMC_CFG_UPDATE 5f4
|
||
|
|
EMC_ADR_CFG 10
|
||
|
|
EMC_REFCTRL 20
|
||
|
|
EMC_PIN 24
|
||
|
|
EMC_TIMING_CONTROL 28
|
||
|
|
EMC_RC 2c
|
||
|
|
EMC_RFC 30
|
||
|
|
EMC_RFCPB 590
|
||
|
|
EMC_RAS 34
|
||
|
|
EMC_RP 38
|
||
|
|
EMC_R2W 3c
|
||
|
|
EMC_W2R 40
|
||
|
|
EMC_R2P 44
|
||
|
|
EMC_W2P 48
|
||
|
|
EMC_CCDMW 5c0
|
||
|
|
EMC_RD_RCD 4c
|
||
|
|
EMC_WR_RCD 50
|
||
|
|
EMC_RRD 54
|
||
|
|
EMC_REXT 58
|
||
|
|
EMC_WDV 5c
|
||
|
|
EMC_QUSE 60
|
||
|
|
EMC_QRST 64
|
||
|
|
EMC_ISSUE_QRST 428
|
||
|
|
EMC_QSAFE 68
|
||
|
|
EMC_RDV 6c
|
||
|
|
EMC_REFRESH 70
|
||
|
|
EMC_BURST_REFRESH_NUM 74
|
||
|
|
EMC_PDEX2WR 78
|
||
|
|
EMC_PDEX2RD 7c
|
||
|
|
EMC_PDEX2CKE 118
|
||
|
|
EMC_PCHG2PDEN 80
|
||
|
|
EMC_ACT2PDEN 84
|
||
|
|
EMC_AR2PDEN 88
|
||
|
|
EMC_RW2PDEN 8c
|
||
|
|
EMC_CKE2PDEN 11c
|
||
|
|
EMC_TXSR 90
|
||
|
|
EMC_TCKE 94
|
||
|
|
EMC_TFAW 98
|
||
|
|
EMC_TRPAB 9c
|
||
|
|
EMC_TCLKSTABLE a0
|
||
|
|
EMC_TCLKSTOP a4
|
||
|
|
EMC_TREFBW a8
|
||
|
|
EMC_TPPD ac
|
||
|
|
EMC_PDEX2MRR b4
|
||
|
|
EMC_ODT_WRITE b0
|
||
|
|
EMC_WEXT b8
|
||
|
|
EMC_RFC_SLR c0
|
||
|
|
EMC_MRS_WAIT_CNT2 c4
|
||
|
|
EMC_MRS_WAIT_CNT c8
|
||
|
|
EMC_MRS cc
|
||
|
|
EMC_EMRS d0
|
||
|
|
EMC_REF d4
|
||
|
|
EMC_PRE d8
|
||
|
|
EMC_NOP dc
|
||
|
|
EMC_SELF_REF e0
|
||
|
|
EMC_DPD e4
|
||
|
|
EMC_MRW e8
|
||
|
|
EMC_MRR ec
|
||
|
|
EMC_CMDQ f0
|
||
|
|
EMC_MC2EMCQ f4
|
||
|
|
EMC_FBIO_SPARE 100
|
||
|
|
EMC_FBIO_CFG5 104
|
||
|
|
EMC_CFG_RSV 120
|
||
|
|
EMC_ACPD_CONTROL 124
|
||
|
|
EMC_MPC 128
|
||
|
|
EMC_EMRS2 12c
|
||
|
|
EMC_EMRS3 130
|
||
|
|
EMC_MRW2 134
|
||
|
|
EMC_MRW3 138
|
||
|
|
EMC_MRW4 13c
|
||
|
|
EMC_MRW5 4a0
|
||
|
|
EMC_MRW6 4a4
|
||
|
|
EMC_MRW7 4a8
|
||
|
|
EMC_MRW8 4ac
|
||
|
|
EMC_MRW9 4b0
|
||
|
|
EMC_MRW10 4b4
|
||
|
|
EMC_MRW11 4b8
|
||
|
|
EMC_MRW12 4bc
|
||
|
|
EMC_MRW13 4c0
|
||
|
|
EMC_MRW14 4c4
|
||
|
|
EMC_MRW15 4d0
|
||
|
|
EMC_CFG_SYNC 4d4
|
||
|
|
EMC_CLKEN_OVERRIDE 140
|
||
|
|
EMC_R2R 144
|
||
|
|
EMC_W2W 148
|
||
|
|
EMC_EINPUT 14c
|
||
|
|
EMC_EINPUT_DURATION 150
|
||
|
|
EMC_PUTERM_EXTRA 154
|
||
|
|
EMC_TCKESR 158
|
||
|
|
EMC_TPD 15c
|
||
|
|
EMC_STAT_CONTROL 160
|
||
|
|
EMC_STAT_STATUS 164
|
||
|
|
EMC_STAT_DRAM_CLOCK_LIMIT_LO 19c
|
||
|
|
EMC_STAT_DRAM_CLOCK_LIMIT_HI 1a0
|
||
|
|
EMC_STAT_DRAM_CLOCKS_LO 1a4
|
||
|
|
EMC_STAT_DRAM_CLOCKS_HI 1a8
|
||
|
|
EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO 1ac
|
||
|
|
EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI 1b0
|
||
|
|
EMC_STAT_DRAM_DEV0_READ_CNT_LO 1b4
|
||
|
|
EMC_STAT_DRAM_DEV0_READ_CNT_HI 1b8
|
||
|
|
EMC_STAT_DRAM_DEV0_READ8_CNT_LO 1bc
|
||
|
|
EMC_STAT_DRAM_DEV0_READ8_CNT_HI 1c0
|
||
|
|
EMC_STAT_DRAM_DEV0_WRITE_CNT_LO 1c4
|
||
|
|
EMC_STAT_DRAM_DEV0_WRITE_CNT_HI 1c8
|
||
|
|
EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO 1cc
|
||
|
|
EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI 1d0
|
||
|
|
EMC_STAT_DRAM_DEV0_REF_CNT_LO 1d4
|
||
|
|
EMC_STAT_DRAM_DEV0_REF_CNT_HI 1d8
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 1dc
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 1e0
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 1e4
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 1e8
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 1ec
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 1f0
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 1f4
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 1f8
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 1fc
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 200
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 204
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 208
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 20c
|
||
|
|
EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 210
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 214
|
||
|
|
EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 218
|
||
|
|
EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO 21c
|
||
|
|
EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI 220
|
||
|
|
EMC_STAT_DRAM_DEV0_DSR 224
|
||
|
|
EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO 228
|
||
|
|
EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI 22c
|
||
|
|
EMC_STAT_DRAM_DEV1_READ_CNT_LO 230
|
||
|
|
EMC_STAT_DRAM_DEV1_READ_CNT_HI 234
|
||
|
|
EMC_STAT_DRAM_DEV1_READ8_CNT_LO 238
|
||
|
|
EMC_STAT_DRAM_DEV1_READ8_CNT_HI 23c
|
||
|
|
EMC_STAT_DRAM_DEV1_WRITE_CNT_LO 240
|
||
|
|
EMC_STAT_DRAM_DEV1_WRITE_CNT_HI 244
|
||
|
|
EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO 248
|
||
|
|
EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI 24c
|
||
|
|
EMC_STAT_DRAM_DEV1_REF_CNT_LO 250
|
||
|
|
EMC_STAT_DRAM_DEV1_REF_CNT_HI 254
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 258
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 25c
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 260
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 264
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 268
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 26c
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 270
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 274
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 278
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 27c
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 280
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 284
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 288
|
||
|
|
EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 28c
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 290
|
||
|
|
EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 294
|
||
|
|
EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO 298
|
||
|
|
EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI 29c
|
||
|
|
EMC_STAT_DRAM_DEV1_DSR 2a0
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO c8c
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI c90
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO c94
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI c98
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO c9c
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI ca0
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO ca4
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI ca8
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO cac
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI cb0
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO cb4
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI cb8
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO cbc
|
||
|
|
EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI cc0
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO cc4
|
||
|
|
EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI cc8
|
||
|
|
EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO ccc
|
||
|
|
EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI cd0
|
||
|
|
EMC_STAT_DRAM_IO_DSR cd4
|
||
|
|
EMC_AUTO_CAL_CONFIG 2a4
|
||
|
|
EMC_AUTO_CAL_CONFIG2 458
|
||
|
|
EMC_AUTO_CAL_CONFIG3 45c
|
||
|
|
EMC_AUTO_CAL_CONFIG4 5b0
|
||
|
|
EMC_AUTO_CAL_CONFIG5 5b4
|
||
|
|
EMC_AUTO_CAL_CONFIG6 5cc
|
||
|
|
EMC_AUTO_CAL_CONFIG7 574
|
||
|
|
EMC_AUTO_CAL_CONFIG8 2dc
|
||
|
|
EMC_AUTO_CAL_VREF_SEL_0 2f8
|
||
|
|
EMC_AUTO_CAL_VREF_SEL_1 300
|
||
|
|
EMC_AUTO_CAL_INTERVAL 2a8
|
||
|
|
EMC_AUTO_CAL_STATUS 2ac
|
||
|
|
EMC_AUTO_CAL_STATUS2 3d4
|
||
|
|
EMC_AUTO_CAL_CHANNEL 464
|
||
|
|
EMC_PMACRO_RX_TERM c48
|
||
|
|
EMC_PMACRO_DQ_TX_DRV c70
|
||
|
|
EMC_PMACRO_CA_TX_DRV c74
|
||
|
|
EMC_PMACRO_CMD_TX_DRV c4c
|
||
|
|
EMC_PMACRO_AUTOCAL_CFG_0 700
|
||
|
|
EMC_PMACRO_AUTOCAL_CFG_1 704
|
||
|
|
EMC_PMACRO_AUTOCAL_CFG_2 708
|
||
|
|
EMC_PMACRO_AUTOCAL_CFG_COMMON c78
|
||
|
|
EMC_PMACRO_ZCTRL c44
|
||
|
|
EMC_XM2COMPPADCTRL 30c
|
||
|
|
EMC_XM2COMPPADCTRL2 578
|
||
|
|
EMC_XM2COMPPADCTRL3 2f4
|
||
|
|
EMC_COMP_PAD_SW_CTRL 57c
|
||
|
|
EMC_REQ_CTRL 2b0
|
||
|
|
EMC_EMC_STATUS 2b4
|
||
|
|
EMC_CFG_2 2b8
|
||
|
|
EMC_CFG_DIG_DLL 2bc
|
||
|
|
EMC_CFG_DIG_DLL_PERIOD 2c0
|
||
|
|
EMC_DIG_DLL_STATUS 2c4
|
||
|
|
EMC_CFG_DIG_DLL_1 2c8
|
||
|
|
EMC_RDV_MASK 2cc
|
||
|
|
EMC_WDV_MASK 2d0
|
||
|
|
EMC_RDV_EARLY_MASK 2d4
|
||
|
|
EMC_RDV_EARLY 2d8
|
||
|
|
EMC_WDV_CHK 4e0
|
||
|
|
EMC_ZCAL_INTERVAL 2e0
|
||
|
|
EMC_ZCAL_WAIT_CNT 2e4
|
||
|
|
EMC_ZCAL_MRW_CMD 2e8
|
||
|
|
EMC_ZQ_CAL 2ec
|
||
|
|
EMC_SCRATCH0 324
|
||
|
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 3c8
|
||
|
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 3cc
|
||
|
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE 3d0
|
||
|
|
EMC_FDPD_CTRL_CMD_NO_RAMP 4d8
|
||
|
|
EMC_SEL_DPD_CTRL 3d8
|
||
|
|
EMC_FDPD_CTRL_DQ 310
|
||
|
|
EMC_FDPD_CTRL_CMD 314
|
||
|
|
EMC_PRE_REFRESH_REQ_CNT 3dc
|
||
|
|
EMC_REFCTRL2 580
|
||
|
|
EMC_FBIO_CFG7 584
|
||
|
|
EMC_DATA_BRLSHFT_0 588
|
||
|
|
EMC_DATA_BRLSHFT_1 58c
|
||
|
|
EMC_DQS_BRLSHFT_0 594
|
||
|
|
EMC_DQS_BRLSHFT_1 598
|
||
|
|
EMC_CMD_BRLSHFT_0 59c
|
||
|
|
EMC_CMD_BRLSHFT_1 5a0
|
||
|
|
EMC_CMD_BRLSHFT_2 5a4
|
||
|
|
EMC_CMD_BRLSHFT_3 5a8
|
||
|
|
EMC_QUSE_BRLSHFT_0 5ac
|
||
|
|
EMC_QUSE_BRLSHFT_1 5b8
|
||
|
|
EMC_QUSE_BRLSHFT_2 5bc
|
||
|
|
EMC_QUSE_BRLSHFT_3 5c4
|
||
|
|
EMC_FBIO_CFG8 5c8
|
||
|
|
EMC_CMD_MAPPING_CMD0_0 380
|
||
|
|
EMC_CMD_MAPPING_CMD0_1 384
|
||
|
|
EMC_CMD_MAPPING_CMD0_2 388
|
||
|
|
EMC_CMD_MAPPING_CMD1_0 38c
|
||
|
|
EMC_CMD_MAPPING_CMD1_1 390
|
||
|
|
EMC_CMD_MAPPING_CMD1_2 394
|
||
|
|
EMC_CMD_MAPPING_CMD2_0 398
|
||
|
|
EMC_CMD_MAPPING_CMD2_1 39c
|
||
|
|
EMC_CMD_MAPPING_CMD2_2 3a0
|
||
|
|
EMC_CMD_MAPPING_CMD3_0 3a4
|
||
|
|
EMC_CMD_MAPPING_CMD3_1 3a8
|
||
|
|
EMC_CMD_MAPPING_CMD3_2 3ac
|
||
|
|
EMC_CMD_MAPPING_BYTE 3b0
|
||
|
|
EMC_DYN_SELF_REF_CONTROL 3e0
|
||
|
|
EMC_TXSRDLL 3e4
|
||
|
|
EMC_CCFIFO_ADDR 3e8
|
||
|
|
EMC_CCFIFO_DATA 3ec
|
||
|
|
EMC_CCFIFO_STATUS 3f0
|
||
|
|
EMC_SWIZZLE_RANK0_BYTE0 404
|
||
|
|
EMC_SWIZZLE_RANK0_BYTE1 408
|
||
|
|
EMC_SWIZZLE_RANK0_BYTE2 40c
|
||
|
|
EMC_SWIZZLE_RANK0_BYTE3 410
|
||
|
|
EMC_SWIZZLE_RANK1_BYTE0 418
|
||
|
|
EMC_SWIZZLE_RANK1_BYTE1 41c
|
||
|
|
EMC_SWIZZLE_RANK1_BYTE2 420
|
||
|
|
EMC_SWIZZLE_RANK1_BYTE3 424
|
||
|
|
EMC_TR_TIMING_0 3b4
|
||
|
|
EMC_TR_CTRL_0 3b8
|
||
|
|
EMC_TR_CTRL_1 3bc
|
||
|
|
EMC_TR_DVFS 460
|
||
|
|
EMC_SWITCH_BACK_CTRL 3c0
|
||
|
|
EMC_TR_RDV 3c4
|
||
|
|
EMC_TR_QPOP 3f4
|
||
|
|
EMC_TR_RDV_MASK 3f8
|
||
|
|
EMC_TR_QSAFE 3fc
|
||
|
|
EMC_TR_QRST 400
|
||
|
|
EMC_IBDLY 468
|
||
|
|
EMC_OBDLY 46c
|
||
|
|
EMC_TXDSRVTTGEN 480
|
||
|
|
EMC_WE_DURATION 48c
|
||
|
|
EMC_WS_DURATION 490
|
||
|
|
EMC_WEV 494
|
||
|
|
EMC_WSV 498
|
||
|
|
EMC_CFG_3 49c
|
||
|
|
EMC_CFG_PIPE_2 554
|
||
|
|
EMC_CFG_PIPE_CLK 558
|
||
|
|
EMC_CFG_PIPE_1 55c
|
||
|
|
EMC_CFG_PIPE 560
|
||
|
|
EMC_QPOP 564
|
||
|
|
EMC_QUSE_WIDTH 568
|
||
|
|
EMC_PUTERM_WIDTH 56c
|
||
|
|
EMC_PROTOBIST_CONFIG_ADR_1 5d0
|
||
|
|
EMC_PROTOBIST_CONFIG_ADR_2 5d4
|
||
|
|
EMC_PROTOBIST_MISC 5d8
|
||
|
|
EMC_PROTOBIST_WDATA_LOWER 5dc
|
||
|
|
EMC_PROTOBIST_WDATA_UPPER 5e0
|
||
|
|
EMC_PROTOBIST_RDATA 5ec
|
||
|
|
EMC_DLL_CFG_0 5e4
|
||
|
|
EMC_DLL_CFG_1 5e8
|
||
|
|
EMC_TRAINING_CMD e00
|
||
|
|
EMC_TRAINING_CTRL e04
|
||
|
|
EMC_TRAINING_STATUS e08
|
||
|
|
EMC_TRAINING_QUSE_CORS_CTRL e0c
|
||
|
|
EMC_TRAINING_QUSE_FINE_CTRL e10
|
||
|
|
EMC_TRAINING_QUSE_CTRL_MISC e14
|
||
|
|
EMC_TRAINING_WRITE_FINE_CTRL e18
|
||
|
|
EMC_TRAINING_WRITE_CTRL_MISC e1c
|
||
|
|
EMC_TRAINING_WRITE_VREF_CTRL e20
|
||
|
|
EMC_TRAINING_READ_FINE_CTRL e24
|
||
|
|
EMC_TRAINING_READ_CTRL_MISC e28
|
||
|
|
EMC_TRAINING_READ_VREF_CTRL e2c
|
||
|
|
EMC_TRAINING_CA_FINE_CTRL e30
|
||
|
|
EMC_TRAINING_CA_CTRL_MISC e34
|
||
|
|
EMC_TRAINING_CA_CTRL_MISC1 e38
|
||
|
|
EMC_TRAINING_CA_VREF_CTRL e3c
|
||
|
|
EMC_TRAINING_CA_TADR_CTRL e40
|
||
|
|
EMC_TRAINING_SETTLE e44
|
||
|
|
EMC_TRAINING_DEBUG_CTRL e48
|
||
|
|
EMC_TRAINING_DEBUG_DQ0 e4c
|
||
|
|
EMC_TRAINING_DEBUG_DQ1 e50
|
||
|
|
EMC_TRAINING_DEBUG_DQ2 e54
|
||
|
|
EMC_TRAINING_DEBUG_DQ3 e58
|
||
|
|
EMC_TRAINING_MPC e5c
|
||
|
|
EMC_TRAINING_PATRAM_CTRL e60
|
||
|
|
EMC_TRAINING_PATRAM_DQ e64
|
||
|
|
EMC_TRAINING_PATRAM_DMI e68
|
||
|
|
EMC_TRAINING_VREF_SETTLE e6c
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0 e70
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1 e74
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2 e78
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3 e7c
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_IB_MISC e80
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0 e84
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1 e88
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2 e8c
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3 e90
|
||
|
|
EMC_TRAINING_RW_EYE_CENTER_OB_MISC e94
|
||
|
|
EMC_TRAINING_RW_OFFSET_IB_BYTE0 e98
|
||
|
|
EMC_TRAINING_RW_OFFSET_IB_BYTE1 e9c
|
||
|
|
EMC_TRAINING_RW_OFFSET_IB_BYTE2 ea0
|
||
|
|
EMC_TRAINING_RW_OFFSET_IB_BYTE3 ea4
|
||
|
|
EMC_TRAINING_RW_OFFSET_IB_MISC ea8
|
||
|
|
EMC_TRAINING_RW_OFFSET_OB_BYTE0 eac
|
||
|
|
EMC_TRAINING_RW_OFFSET_OB_BYTE1 eb0
|
||
|
|
EMC_TRAINING_RW_OFFSET_OB_BYTE2 eb4
|
||
|
|
EMC_TRAINING_RW_OFFSET_OB_BYTE3 eb8
|
||
|
|
EMC_TRAINING_RW_OFFSET_OB_MISC ebc
|
||
|
|
EMC_TRAINING_OPT_CA_VREF ec0
|
||
|
|
EMC_TRAINING_OPT_DQ_OB_VREF ec4
|
||
|
|
EMC_TRAINING_OPT_DQ_IB_VREF_RANK0 ec8
|
||
|
|
EMC_TRAINING_OPT_DQ_IB_VREF_RANK1 ecc
|
||
|
|
EMC_TRAINING_QUSE_VREF_CTRL ed0
|
||
|
|
EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 ed4
|
||
|
|
EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 ed8
|
||
|
|
EMC_TRAINING_DRAMC_TIMING edc
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_0 600
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_1 604
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_2 608
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_3 60c
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_4 610
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK0_5 614
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_0 620
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_1 624
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_2 628
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_3 62c
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_4 630
|
||
|
|
EMC_PMACRO_QUSE_DDLL_RANK1_5 634
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 640
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 644
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 648
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 64c
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 650
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 654
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 660
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 664
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 668
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 66c
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 670
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 674
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 680
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 684
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 688
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 68c
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 690
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 694
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 6a0
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 6a4
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 6a8
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 6ac
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 6b0
|
||
|
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 6b4
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 6c0
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 6c4
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 6c8
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 6cc
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4 6d0
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5 6d4
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 6e0
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 6e4
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 6e8
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 6ec
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4 6f0
|
||
|
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5 6f4
|
||
|
|
EMC_PMACRO_TX_PWRD_0 720
|
||
|
|
EMC_PMACRO_TX_PWRD_1 724
|
||
|
|
EMC_PMACRO_TX_PWRD_2 728
|
||
|
|
EMC_PMACRO_TX_PWRD_3 72c
|
||
|
|
EMC_PMACRO_TX_PWRD_4 730
|
||
|
|
EMC_PMACRO_TX_PWRD_5 734
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_0 740
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_1 744
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_3 74c
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_2 748
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_4 750
|
||
|
|
EMC_PMACRO_TX_SEL_CLK_SRC_5 754
|
||
|
|
EMC_PMACRO_DDLL_BYPASS 760
|
||
|
|
EMC_PMACRO_DDLL_PWRD_0 770
|
||
|
|
EMC_PMACRO_DDLL_PWRD_1 774
|
||
|
|
EMC_PMACRO_DDLL_PWRD_2 778
|
||
|
|
EMC_PMACRO_CMD_CTRL_0 780
|
||
|
|
EMC_PMACRO_CMD_CTRL_1 784
|
||
|
|
EMC_PMACRO_CMD_CTRL_2 788
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 800
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 804
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 808
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 80c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 810
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 814
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 818
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 81c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 820
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 824
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 828
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 82c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 830
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 834
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 838
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 83c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 840
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 844
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 848
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 84c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 850
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 854
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 858
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 85c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 860
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 864
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 868
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 86c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 870
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 874
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 878
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 87c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 880
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 884
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 888
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 88c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 890
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 894
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 898
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 89c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 8a0
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 8a4
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 8a8
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 8ac
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 8b0
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 8b4
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 8b8
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 8bc
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 900
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 904
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 908
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 90c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 910
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 914
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 918
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 91c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 920
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 924
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 928
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 92c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 930
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 934
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 938
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 93c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 940
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 944
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 948
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 94c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 950
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 954
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 958
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 95c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 960
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 964
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 968
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 96c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 970
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 974
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 978
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 97c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 980
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 984
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 988
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 98c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 990
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 994
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 998
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 99c
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 9a0
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 9a4
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 9a8
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 9ac
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 9b0
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 9b4
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 9b8
|
||
|
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 9bc
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 a00
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 a04
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 a08
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 a10
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 a14
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 a18
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 a20
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 a24
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 a28
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 a30
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 a34
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 a38
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 a40
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 a44
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 a48
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 a50
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 a54
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 a58
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 a60
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 a64
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 a68
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 a70
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 a74
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 a78
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0 a80
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1 a84
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2 a88
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0 a90
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1 a94
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2 a98
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0 aa0
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1 aa4
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2 aa8
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0 ab0
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1 ab4
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2 ab8
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 b00
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 b04
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 b08
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 b10
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 b14
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 b18
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 b20
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 b24
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 b28
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 b30
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 b34
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 b38
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 b40
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 b44
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 b48
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 b50
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 b54
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 b58
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 b60
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 b64
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 b68
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 b70
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 b74
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 b78
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0 b80
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1 b84
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2 b88
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0 b90
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1 b94
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2 b98
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0 ba0
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1 ba4
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2 ba8
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0 bb0
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1 bb4
|
||
|
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2 bb8
|
||
|
|
EMC_PMACRO_IB_VREF_DQ_0 be0
|
||
|
|
EMC_PMACRO_IB_VREF_DQ_1 be4
|
||
|
|
EMC_PMACRO_IB_VREF_DQ_2 be8
|
||
|
|
EMC_PMACRO_IB_VREF_DQS_0 bf0
|
||
|
|
EMC_PMACRO_IB_VREF_DQS_1 bf4
|
||
|
|
EMC_PMACRO_IB_VREF_DQS_2 bf8
|
||
|
|
EMC_PMACRO_IB_RXRT cf4
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_0 c00
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_1 c04
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_2 c08
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_3 c0c
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_4 c10
|
||
|
|
EMC_PMACRO_DDLL_LONG_CMD_5 c14
|
||
|
|
EMC_PMACRO_DDLL_SHORT_CMD_0 c20
|
||
|
|
EMC_PMACRO_DDLL_SHORT_CMD_1 c24
|
||
|
|
EMC_PMACRO_DDLL_SHORT_CMD_2 c28
|
||
|
|
EMC_PMACRO_CFG_PM_GLOBAL_0 c30
|
||
|
|
EMC_PMACRO_VTTGEN_CTRL_0 c34
|
||
|
|
EMC_PMACRO_VTTGEN_CTRL_1 c38
|
||
|
|
EMC_PMACRO_VTTGEN_CTRL_2 cf0
|
||
|
|
EMC_PMACRO_BG_BIAS_CTRL_0 c3c
|
||
|
|
EMC_PMACRO_PAD_CFG_CTRL c40
|
||
|
|
EMC_PMACRO_CMD_PAD_RX_CTRL c50
|
||
|
|
EMC_PMACRO_DATA_PAD_RX_CTRL c54
|
||
|
|
EMC_PMACRO_CMD_RX_TERM_MODE c58
|
||
|
|
EMC_PMACRO_DATA_RX_TERM_MODE c5c
|
||
|
|
EMC_PMACRO_CMD_PAD_TX_CTRL c60
|
||
|
|
EMC_PMACRO_DATA_PAD_TX_CTRL c64
|
||
|
|
EMC_PMACRO_COMMON_PAD_TX_CTRL c68
|
||
|
|
EMC_PMACRO_BRICK_MAPPING_0 c80
|
||
|
|
EMC_PMACRO_BRICK_MAPPING_1 c84
|
||
|
|
EMC_PMACRO_BRICK_MAPPING_2 c88
|
||
|
|
EMC_PMACRO_DDLLCAL_CAL ce0
|
||
|
|
EMC_PMACRO_DDLL_OFFSET ce4
|
||
|
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET ce8
|
||
|
|
EMC_PMACRO_BRICK_CTRL_RFU1 330
|
||
|
|
EMC_PMACRO_BRICK_CTRL_RFU2 334
|
||
|
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD 318
|
||
|
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD 31c
|
||
|
|
EMC_PMACRO_TRAINING_CTRL_0 cf8
|
||
|
|
EMC_PMACRO_TRAINING_CTRL_1 cfc
|
||
|
|
EMC_PMC_SCRATCH1 440
|
||
|
|
EMC_PMC_SCRATCH2 444
|
||
|
|
EMC_PMC_SCRATCH3 448
|