2018-03-27 00:04:16 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-03-07 01:11:46 +00:00
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#ifndef _T210_H_
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#define _T210_H_
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#include "types.h"
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#define HOST1X_BASE 0x50000000
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#define DISPLAY_A_BASE 0x54200000
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#define DSI_BASE 0x54300000
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#define VIC_BASE 0x54340000
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2018-03-14 23:26:19 +00:00
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#define TSEC_BASE 0x54500000
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#define SOR1_BASE 0x54580000
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2018-03-07 01:11:46 +00:00
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#define TMR_BASE 0x60005000
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#define CLOCK_BASE 0x60006000
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2018-03-14 23:26:19 +00:00
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#define FLOW_CTLR_BASE 0x60007000
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2018-03-07 01:11:46 +00:00
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#define SYSREG_BASE 0x6000C000
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2018-03-14 23:26:19 +00:00
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#define SB_BASE (SYSREG_BASE + 0x200)
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2018-03-07 01:11:46 +00:00
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#define GPIO_BASE 0x6000D000
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#define GPIO_1_BASE (GPIO_BASE)
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#define GPIO_2_BASE (GPIO_BASE + 0x100)
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#define GPIO_3_BASE (GPIO_BASE + 0x200)
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2018-05-01 06:15:48 +01:00
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#define GPIO_4_BASE (GPIO_BASE + 0x300)
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#define GPIO_5_BASE (GPIO_BASE + 0x400)
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2018-03-07 01:11:46 +00:00
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#define GPIO_6_BASE (GPIO_BASE + 0x500)
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2018-05-01 06:15:48 +01:00
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#define GPIO_7_BASE (GPIO_BASE + 0x600)
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#define GPIO_8_BASE (GPIO_BASE + 0x700)
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2018-03-14 23:26:19 +00:00
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#define EXCP_VEC_BASE 0x6000F000
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2018-05-01 06:15:48 +01:00
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#define APB_MISC_BASE 0x70000000
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2018-03-07 01:11:46 +00:00
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#define PINMUX_AUX_BASE 0x70003000
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#define UART_BASE 0x70006000
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#define PMC_BASE 0x7000E400
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#define SYSCTR0_BASE 0x7000F000
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#define FUSE_BASE 0x7000F800
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2018-05-01 06:15:48 +01:00
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#define KFUSE_BASE 0x7000FC00
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#define SE_BASE 0x70012000
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2018-03-07 01:11:46 +00:00
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#define MC_BASE 0x70019000
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#define EMC_BASE 0x7001B000
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#define MIPI_CAL_BASE 0x700E3000
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#define I2S_BASE 0x702D1000
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#define _REG(base, off) *(vu32 *)((base) + (off))
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#define HOST1X(off) _REG(HOST1X_BASE, off)
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#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
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#define DSI(off) _REG(DSI_BASE, off)
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#define VIC(off) _REG(VIC_BASE, off)
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2018-03-14 23:26:19 +00:00
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#define TSEC(off) _REG(TSEC_BASE, off)
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#define SOR1(off) _REG(SOR1_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define TMR(off) _REG(TMR_BASE, off)
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#define CLOCK(off) _REG(CLOCK_BASE, off)
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2018-03-14 23:26:19 +00:00
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#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define SYSREG(off) _REG(SYSREG_BASE, off)
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2018-03-14 23:26:19 +00:00
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#define SB(off) _REG(SB_BASE, off)
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2018-05-01 06:15:48 +01:00
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#define GPIO(off) _REG(GPIO_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define GPIO_1(off) _REG(GPIO_1_BASE, off)
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#define GPIO_2(off) _REG(GPIO_2_BASE, off)
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#define GPIO_3(off) _REG(GPIO_3_BASE, off)
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2018-05-01 06:15:48 +01:00
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#define GPIO_4(off) _REG(GPIO_4_BASE, off)
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#define GPIO_5(off) _REG(GPIO_5_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define GPIO_6(off) _REG(GPIO_6_BASE, off)
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2018-05-01 06:15:48 +01:00
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#define GPIO_7(off) _REG(GPIO_7_BASE, off)
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#define GPIO_8(off) _REG(GPIO_8_BASE, off)
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2018-03-14 23:26:19 +00:00
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#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
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2018-05-01 06:15:48 +01:00
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#define APB_MISC(off) _REG(APB_MISC_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
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#define PMC(off) _REG(PMC_BASE, off)
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#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
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#define FUSE(off) _REG(FUSE_BASE, off)
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2018-05-01 06:15:48 +01:00
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#define KFUSE(off) _REG(KFUSE_BASE, off)
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#define SE(off) _REG(SE_BASE, off)
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2018-03-07 01:11:46 +00:00
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#define MC(off) _REG(MC_BASE, off)
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#define EMC(off) _REG(EMC_BASE, off)
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#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
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#define I2S(off) _REG(I2S_BASE, off)
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/*! System registers. */
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#define AHB_ARBITRATION_XBAR_CTRL 0xE0
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2018-03-14 23:26:19 +00:00
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/*! Secure boot registers. */
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2018-05-01 06:15:48 +01:00
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#define SB_CSR 0x0
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2018-03-14 23:26:19 +00:00
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#define SB_AA64_RESET_LOW 0x30
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#define SB_AA64_RESET_HIGH 0x34
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2018-03-07 01:11:46 +00:00
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/*! SYSCTR0 registers. */
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#define SYSCTR0_CNTFID0 0x20
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#endif
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