2018-03-27 00:04:16 +01:00
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/*
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2018-08-05 12:40:32 +01:00
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 st4rk
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2022-01-20 10:13:35 +00:00
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* Copyright (c) 2018-2022 CTCaer
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2018-08-05 12:40:32 +01:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2018-03-27 00:04:16 +01:00
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2018-03-14 23:26:19 +00:00
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#ifndef _PMC_H_
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#define _PMC_H_
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2020-07-17 22:42:53 +01:00
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#include <utils/types.h>
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2018-03-14 23:26:19 +00:00
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/*! PMC registers. */
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2022-05-08 03:22:41 +01:00
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#define APBDEV_PMC_CNTRL 0x0
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#define PMC_CNTRL_RTC_CLK_DIS BIT(1)
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#define PMC_CNTRL_RTC_RST BIT(2)
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define PMC_CNTRL_LATCHWAKE_EN BIT(5)
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#define PMC_CNTRL_BLINK_EN BIT(7)
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#define PMC_CNTRL_PWRREQ_OE BIT(9)
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#define PMC_CNTRL_SYSCLK_OE BIT(11)
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#define PMC_CNTRL_PWRGATE_DIS BIT(12)
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#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14)
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#define PMC_CNTRL_CPUPWRREQ_OE BIT(16)
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#define PMC_CNTRL_FUSE_OVERRIDE BIT(18)
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#define PMC_CNTRL_SHUTDOWN_OE BIT(22)
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#define APBDEV_PMC_SEC_DISABLE 0x4
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#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
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#define APBDEV_PMC_PWRGATE_STATUS 0x38
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#define APBDEV_PMC_NO_IOPOWER 0x44
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#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12)
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#define PMC_NO_IOPOWER_AUDIO_HV BIT(18)
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#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_SCRATCH0 0x50
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#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29)
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#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30)
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_FASTBOOT | \
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PMC_SCRATCH0_MODE_PAYLOAD)
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#define APBDEV_PMC_BLINK_TIMER 0x40
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#define PMC_BLINK_ON(n) ((n & 0x7FFF))
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#define PMC_BLINK_FORCE BIT(15)
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#define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16)
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#define APBDEV_PMC_SCRATCH1 0x54
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#define APBDEV_PMC_SCRATCH20 0xA0
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#define APBDEV_PMC_SECURE_SCRATCH4 0xC0
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#define APBDEV_PMC_SECURE_SCRATCH5 0xC4
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#define APBDEV_PMC_PWR_DET_VAL 0xE4
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#define PMC_PWR_DET_SDMMC1_IO_EN BIT(12)
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#define PMC_PWR_DET_AUDIO_HV BIT(18)
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#define PMC_PWR_DET_GPIO_IO_EN BIT(21)
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#define APBDEV_PMC_DDR_PWR 0xE8
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#define APBDEV_PMC_USB_AO 0xF0
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#define APBDEV_PMC_CRYPTO_OP 0xF4
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#define PMC_CRYPTO_OP_SE_ENABLE 0
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#define PMC_CRYPTO_OP_SE_DISABLE 1
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#define APBDEV_PMC_SCRATCH33 0x120
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#define APBDEV_PMC_SCRATCH37 0x130
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#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN"
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#define APBDEV_PMC_SCRATCH40 0x13C
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#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
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#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22)
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#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
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#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2)
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#define PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN BIT(10)
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2022-05-09 04:08:39 +01:00
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#define PMC_CLK_OUT_CNTRL_CLK3_FORCE_EN BIT(18)
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#define PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(src) (((src) & 3) << 6)
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#define PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(src) (((src) & 3) << 14)
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#define PMC_CLK_OUT_CNTRL_CLK3_SRC_SEL(src) (((src) & 3) << 22)
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#define OSC_DIV1 0
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#define OSC_DIV2 1
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#define OSC_DIV4 2
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#define OSC_CAR 3
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2022-05-08 03:22:41 +01:00
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#define APBDEV_PMC_RST_STATUS 0x1B4
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#define PMC_RST_STATUS_MASK 7
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#define PMC_RST_STATUS_POR 0
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#define PMC_RST_STATUS_WATCHDOG 1
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#define PMC_RST_STATUS_SENSOR 2
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#define PMC_RST_STATUS_SW_MAIN 3
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#define PMC_RST_STATUS_LP0 4
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#define PMC_RST_STATUS_AOTAG 5
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#define APBDEV_PMC_IO_DPD_REQ 0x1B8
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#define PMC_IO_DPD_REQ_DPD_OFF BIT(30)
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#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
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#define APBDEV_PMC_VDDP_SEL 0x1CC
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#define APBDEV_PMC_DDR_CFG 0x1D0
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#define APBDEV_PMC_SECURE_SCRATCH6 0x224
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#define APBDEV_PMC_SECURE_SCRATCH7 0x228
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#define APBDEV_PMC_SCRATCH45 0x234
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#define APBDEV_PMC_SCRATCH46 0x238
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#define APBDEV_PMC_SCRATCH49 0x244
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#define APBDEV_PMC_TSC_MULT 0x2B4
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#define APBDEV_PMC_SEC_DISABLE2 0x2C4
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#define APBDEV_PMC_WEAK_BIAS 0x2C8
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#define APBDEV_PMC_REG_SHORT 0x2CC
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#define APBDEV_PMC_SEC_DISABLE3 0x2D8
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#define APBDEV_PMC_SECURE_SCRATCH21 0x334
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#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4)
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#define APBDEV_PMC_SECURE_SCRATCH32 0x360
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#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
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#define APBDEV_PMC_CNTRL2 0x440
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#define PMC_CNTRL2_WAKE_INT_EN BIT(0)
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#define PMC_CNTRL2_WAKE_DET_EN BIT(9)
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#define PMC_CNTRL2_SYSCLK_ORRIDE BIT(10)
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#define PMC_CNTRL2_HOLD_CKE_LOW_EN BIT(12)
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#define PMC_CNTRL2_ALLOW_PULSE_WAKE BIT(14)
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#define APBDEV_PMC_IO_DPD3_REQ 0x45C
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#define APBDEV_PMC_IO_DPD4_REQ 0x464
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#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
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#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
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#define APBDEV_PMC_DDR_CNTRL 0x4E4
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#define APBDEV_PMC_SEC_DISABLE4 0x5B0
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#define APBDEV_PMC_SEC_DISABLE5 0x5B4
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#define APBDEV_PMC_SEC_DISABLE6 0x5B8
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#define APBDEV_PMC_SEC_DISABLE7 0x5BC
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#define APBDEV_PMC_SEC_DISABLE8 0x5C0
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#define APBDEV_PMC_SEC_DISABLE9 0x5C4
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#define APBDEV_PMC_SEC_DISABLE10 0x5C8
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#define APBDEV_PMC_SCRATCH188 0x810
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#define APBDEV_PMC_SCRATCH190 0x818
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#define APBDEV_PMC_SCRATCH200 0x840
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2022-01-15 23:03:24 +00:00
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#define APBDEV_PMC_SECURE_SCRATCH108 0xB08
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#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C
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#define APBDEV_PMC_SECURE_SCRATCH110 0xB10
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2022-05-08 03:22:41 +01:00
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// Only in T210B01.
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#define APBDEV_PMC_LED_BREATHING_CTRL 0xB48
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#define PMC_LED_BREATHING_CTRL_ENABLE BIT(0)
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#define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1)
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#define APBDEV_PMC_LED_BREATHING_SLOPE_STEPS 0xB4C
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#define APBDEV_PMC_LED_BREATHING_ON_COUNTER 0xB50
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#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER1 0xB54
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#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER0 0xB58
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#define PMC_LED_BREATHING_COUNTER_HZ 32768
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#define APBDEV_PMC_LED_BREATHING_STATUS 0xB5C
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#define PMC_LED_BREATHING_FSM_STATUS_MASK 0x7
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#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8
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#define PMC_TZRAM_PWR_CNTRL_SD BIT(0)
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#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC
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#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0
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#define PMC_TZRAM_DISABLE_REG_WRITE BIT(0)
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#define PMC_TZRAM_DISABLE_REG_READ BIT(1)
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2018-03-14 23:26:19 +00:00
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2020-12-26 14:48:00 +00:00
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typedef enum _pmc_sec_lock_t
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{
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PMC_SEC_LOCK_MISC = BIT(0),
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PMC_SEC_LOCK_LP0_PARAMS = BIT(1),
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PMC_SEC_LOCK_RST_VECTOR = BIT(2),
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PMC_SEC_LOCK_CARVEOUTS = BIT(3),
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PMC_SEC_LOCK_TZ_CMAC_W = BIT(4),
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PMC_SEC_LOCK_TZ_CMAC_R = BIT(5),
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PMC_SEC_LOCK_TZ_KEK_W = BIT(6),
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PMC_SEC_LOCK_TZ_KEK_R = BIT(7),
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PMC_SEC_LOCK_SE_SRK = BIT(8),
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} pmc_sec_lock_t;
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2020-12-26 15:20:26 +00:00
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typedef enum _pmc_power_rail_t
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{
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POWER_RAIL_CRAIL = 0,
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POWER_RAIL_3D0 = 1,
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POWER_RAIL_VENC = 2,
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POWER_RAIL_PCIE = 3,
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POWER_RAIL_VDEC = 4,
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POWER_RAIL_L2C = 5,
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POWER_RAIL_MPE = 6,
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POWER_RAIL_HEG = 7,
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POWER_RAIL_SATA = 8,
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POWER_RAIL_CE1 = 9,
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POWER_RAIL_CE2 = 10,
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POWER_RAIL_CE3 = 11,
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POWER_RAIL_CELP = 12,
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POWER_RAIL_3D1 = 13,
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POWER_RAIL_CE0 = 14,
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POWER_RAIL_C0NC = 15,
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POWER_RAIL_C1NC = 16,
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POWER_RAIL_SOR = 17,
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POWER_RAIL_DIS = 18,
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POWER_RAIL_DISB = 19,
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POWER_RAIL_XUSBA = 20,
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POWER_RAIL_XUSBB = 21,
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POWER_RAIL_XUSBC = 22,
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POWER_RAIL_VIC = 23,
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POWER_RAIL_IRAM = 24,
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POWER_RAIL_NVDEC = 25,
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POWER_RAIL_NVJPG = 26,
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POWER_RAIL_AUD = 27,
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POWER_RAIL_DFD = 28,
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POWER_RAIL_VE2 = 29
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} pmc_power_rail_t;
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2020-12-26 14:48:00 +00:00
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void pmc_scratch_lock(pmc_sec_lock_t lock_mask);
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2020-12-26 15:20:26 +00:00
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int pmc_enable_partition(pmc_power_rail_t part, u32 enable);
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2020-07-17 22:42:53 +01:00
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2018-03-14 23:26:19 +00:00
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#endif
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