mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-22 18:06:40 +00:00
bdk: timer: add timer/watchdog driver
This commit is contained in:
CTCaer
parent
b65b2d7f71
commit
061e10152f
6 changed files with 192 additions and 66 deletions
7
Makefile
7
Makefile
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@ -31,9 +31,10 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \
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# Hardware.
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OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
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bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o mc.o sdram.o \
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pinmux.o pmc.o se.o smmu.o tsec.o uart.o \
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fuse.o kfuse.o minerva.o \
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bpmp.o ccplex.o clock.o di.o i2c.o irq.o timer.o \
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mc.o sdram.o minerva.o \
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gpio.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \
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fuse.o kfuse.o \
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sdmmc.o sdmmc_driver.o emmc.o sd.o emummc.o \
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bq24193.o max17050.o max7762x.o max77620-rtc.o \
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hw_init.o \
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114
bdk/soc/timer.c
Normal file
114
bdk/soc/timer.c
Normal file
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@ -0,0 +1,114 @@
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/*
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* Timer/Watchdog driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <soc/bpmp.h>
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#include <soc/irq.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <utils/types.h>
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#define EXCP_TYPE_ADDR 0x4003FFF8
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#define EXCP_TYPE_WDT 0x544457 // "WDT".
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u32 get_tmr_s()
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{
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(void)RTC(APBDEV_RTC_MILLI_SECONDS);
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return (u32)RTC(APBDEV_RTC_SECONDS);
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
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return (u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
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}
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u32 get_tmr_us()
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{
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return (u32)TMR(TIMERUS_CNTR_1US);
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}
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void msleep(u32 ms)
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{
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#ifdef USE_RTC_TIMER
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u32 start = (u32)RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
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// Casting to u32 is important!
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while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
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;
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#else
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bpmp_msleep(ms);
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#endif
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}
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void usleep(u32 us)
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{
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#ifdef USE_RTC_TIMER
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u32 start = (u32)TMR(TIMERUS_CNTR_1US);
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// Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately.
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if ((start + us) < start)
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bpmp_usleep(us);
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else
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while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important!
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;
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#else
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bpmp_usleep(us);
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#endif
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}
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void timer_usleep(u32 us)
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{
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TMR(TIMER_TMR8_TMR_PTV) = TIMER_EN | us;
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irq_wait_event(IRQ_TMR8);
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TMR(TIMER_TMR8_TMR_PCR) = TIMER_INTR_CLR;
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}
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void watchdog_start(u32 us, u32 mode)
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{
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// WDT4 is for BPMP.
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN | us;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | mode;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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}
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void watchdog_end()
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{
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// WDT4 is for BPMP.
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TMR(TIMER_TMR9_TMR_PTV) = 0;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; // Re-arm to clear any interrupts.
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TMR(TIMER_WDT4_COMMAND) = TIMER_CNT_DISABLE;
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}
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void watchdog_handle()
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{
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// Disable watchdog and clear its interrupts.
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watchdog_end();
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// Set watchdog magic.
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*(u32 *)EXCP_TYPE_ADDR = EXCP_TYPE_WDT;
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}
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bool watchdog_fired()
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{
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// Return if watchdog got fired. User handles clearing.
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return (*(u32 *)EXCP_TYPE_ADDR == EXCP_TYPE_WDT);
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}
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62
bdk/soc/timer.h
Normal file
62
bdk/soc/timer.h
Normal file
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@ -0,0 +1,62 @@
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/*
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* Timer/Watchdog driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TIMER_H_
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#define _TIMER_H_
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#include <utils/types.h>
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// TMR registers.
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#define TIMERUS_CNTR_1US (0x10 + 0x0)
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#define TIMERUS_USEC_CFG (0x10 + 0x4)
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#define TIMER_TMR8_TMR_PTV 0x78
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#define TIMER_TMR9_TMR_PTV 0x80
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#define TIMER_PER_EN BIT(30)
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#define TIMER_EN BIT(31)
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#define TIMER_TMR8_TMR_PCR 0x7C
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#define TIMER_TMR9_TMR_PCR 0x8C
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#define TIMER_INTR_CLR BIT(30)
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// WDT registers.
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#define TIMER_WDT4_CONFIG (0x100 + 0x80)
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#define TIMER_SRC(TMR) ((TMR) & 0xF)
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#define TIMER_PER(PER) (((PER) & 0xFF) << 4)
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#define TIMER_IRQENABL_EN BIT(12)
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#define TIMER_FIQENABL_EN BIT(13)
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#define TIMER_SYSRESET_EN BIT(14)
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#define TIMER_PMCRESET_EN BIT(15)
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#define TIMER_WDT4_COMMAND (0x108 + 0x80)
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#define TIMER_START_CNT BIT(0)
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#define TIMER_CNT_DISABLE BIT(1)
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#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
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#define TIMER_MAGIC_PTRN 0xC45A
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u32 get_tmr_us();
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u32 get_tmr_ms();
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u32 get_tmr_s();
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void usleep(u32 us);
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void msleep(u32 ms);
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void timer_usleep(u32 us);
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void watchdog_start(u32 us, u32 mode);
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void watchdog_end();
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void watchdog_handle();
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bool watchdog_fired();
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#endif
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@ -24,14 +24,13 @@
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#include <soc/hw_init.h>
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#include <soc/i2c.h>
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#include <soc/pmc.h>
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#include <soc/timer.h>
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#include <soc/t210.h>
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#include <storage/sd.h>
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#include <utils/util.h>
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#define USE_RTC_TIMER
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extern volatile nyx_storage_t *nyx_str;
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u8 bit_count(u32 val)
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{
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u8 cnt = 0;
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@ -103,51 +102,6 @@ u64 sqrt64(u64 num)
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return square_root;
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}
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u32 get_tmr_s()
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{
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return RTC(APBDEV_RTC_SECONDS);
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
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return (RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000));
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}
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u32 get_tmr_us()
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{
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return TMR(TIMERUS_CNTR_1US);
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}
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void msleep(u32 ms)
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{
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#ifdef USE_RTC_TIMER
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u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000);
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// Casting to u32 is important!
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while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms)
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;
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#else
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bpmp_msleep(ms);
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#endif
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}
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void usleep(u32 us)
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{
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#ifdef USE_RTC_TIMER
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u32 start = TMR(TIMERUS_CNTR_1US);
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// Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately.
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if ((start + us) < start)
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bpmp_usleep(us);
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else
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while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important!
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;
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#else
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bpmp_usleep(us);
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#endif
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}
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
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{
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for(u32 i = 0; i < num_ops; i++)
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@ -195,14 +149,14 @@ void panic(u32 val)
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{
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// Set panic code.
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PMC(APBDEV_PMC_SCRATCH200) = val;
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//PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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while (true)
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usleep(1);
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// Disable SE.
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//PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE;
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// Immediately cause a full system reset.
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watchdog_start(0, TIMER_PMCRESET_EN);
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while (true);
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}
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void power_set_state(power_state_t state)
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@ -231,7 +185,7 @@ void power_set_state(power_state_t state)
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break;
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case POWER_OFF:
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// Initiate power down sequence and do not generate a reset (regulators retain state).
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// Initiate power down sequence and do not generate a reset (regulators retain state after POR).
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
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break;
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@ -246,7 +200,7 @@ void power_set_state(power_state_t state)
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reg |= MAX77620_ONOFFCNFG2_SFT_RST_WK;
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, reg);
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// Initiate power down sequence and generate a reset (regulators' state resets).
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// Initiate power down sequence and generate a reset (regulators' state resets after POR).
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_SFT_RST);
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break;
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}
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@ -89,12 +89,6 @@ u64 sqrt64(u64 num);
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops);
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u32 crc32_calc(u32 crc, const u8 *buf, u32 len);
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u32 get_tmr_us();
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u32 get_tmr_ms();
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u32 get_tmr_s();
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void usleep(u32 us);
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void msleep(u32 ms);
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void panic(u32 val);
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void power_set_state(power_state_t state);
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void power_set_state_ex(void *param);
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@ -33,7 +33,8 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \
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# Hardware.
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OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \
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bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \
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bpmp.o ccplex.o clock.o di.o i2c.o irq.o timer.o \
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gpio.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \
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fuse.o kfuse.o \
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mc.o sdram.o minerva.o ramdisk.o \
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sdmmc.o sdmmc_driver.o emmc.o sd.o nx_emmc_bis.o \
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